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| author | Julian Blake Kongslie | 2022-02-18 16:22:49 -0800 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-02-18 16:22:49 -0800 |
| commit | 516cc6baacf47e1c199cf0d128b6694d995859ac (patch) | |
| tree | 9c4a11a268e8a86cb6f63a16d5df90540936644a /tcl/init.tcl | |
| parent | Limit size of reset counter to something realistic. (diff) | |
| download | simple-memory-controller-516cc6baacf47e1c199cf0d128b6694d995859ac.tar.xz | |
Explicitly disable signaltap compilation.
Diffstat (limited to 'tcl/init.tcl')
| -rw-r--r-- | tcl/init.tcl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcl/init.tcl b/tcl/init.tcl index 2f29aec..c63734c 100644 --- a/tcl/init.tcl +++ b/tcl/init.tcl | |||
| @@ -6,6 +6,7 @@ set_global_assignment -name TOP_LEVEL_ENTITY top | |||
| 6 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 | 6 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 |
| 7 | set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1" | 7 | set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1" |
| 8 | set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 | 8 | set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 |
| 9 | set_global_assignment -name ENABLE_SIGNALTAP OFF | ||
| 9 | 10 | ||
| 10 | proc pin {net loc} { | 11 | proc pin {net loc} { |
| 11 | set_location_assignment -to $net "PIN_$loc" | 12 | set_location_assignment -to $net "PIN_$loc" |