hdl/result_printer.sv


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module result_printer
    (   input   bit         clock
    ,   input   bit         resetn

    ,   output  bit         result_ready
    ,   input   bit         result_valid
    ,   input   bit [15:0]  result_data

    ,   input   bit         echo_ready
    ,   output  bit         echo_valid
    ,   output  bit [7:0]   echo_data
    );

    bit         hold_valid;
    bit [15:0]  hold;

    (* syn_encoding = "one-hot" *) enum
        {   DIGIT_1
        ,   DIGIT_2
        ,   DIGIT_3
        ,   DIGIT_4
        } state;

    always @(posedge clock) begin
        if (!resetn) begin
            result_ready = 0;
            echo_valid = 0;
            echo_data = 0;
            hold_valid = 0;
            hold = 0;
            state = state.first;
        end else begin
            if (echo_ready) echo_valid = 0;
            if (result_ready && result_valid) begin
                hold_valid = 1;
                hold = result_data;
            end

            if (hold_valid && !echo_valid) begin
                echo_valid = 1;
                echo_data = hold[15:12];
                hold = hold << 4;
                if (echo_data < 10)
                    echo_data = echo_data + "0";
                else
                    echo_data = echo_data + "A" - 10;
                state = state.next;
                if (state == state.first) hold_valid = 0;
            end

            result_ready = !hold_valid;
        end
    end

endmodule