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module top
( input bit clock
, input bit resetn
, output bit ram_resetn
, output bit [1:0] ram_csn
, output bit ram_clkp
, output bit ram_clkn
, inout bit ram_rwds
, inout bit [7:0] ram_data
);
bit rx_ready;
bit rx_valid;
bit [7:0] rx_data;
bit tx_ready;
bit tx_valid;
bit [7:0] tx_data;
bit echo_in0_ready;
bit echo_in0_valid;
bit [7:0] echo_in0_data;
bit echo_in1_ready;
bit echo_in1_valid;
bit [7:0] echo_in1_data;
bit command_ready;
bit command_valid;
bit [23:0] command_address;
bit command_write;
bit [15:0] command_data;
bit result_ready;
bit result_valid;
bit [15:0] result_data;
bit ram_rwds_oe;
bit ram_rwds_out;
assign ram_rwds = ram_rwds_oe ? ram_rwds_out : 'bZ;
bit ram_data_oe;
bit [7:0] ram_data_out;
assign ram_data = ram_data_oe ? ram_data_out : 'bZ;
alt_jtag_atlantic
#( .INSTANCE_ID(0)
, .LOG2_RXFIFO_DEPTH(6)
, .LOG2_TXFIFO_DEPTH(6)
, .SLD_AUTO_INSTANCE_INDEX("NO")
) jtag
( .clk(clock)
, .rst_n(resetn)
, .r_dat(tx_data)
, .r_val(tx_valid)
, .r_ena(tx_ready)
, .t_dat(rx_data)
, .t_dav(rx_ready)
, .t_ena(rx_valid)
);
echo_arbiter arb
( .clock(clock)
, .resetn(resetn)
, .in0_ready(echo_in0_ready)
, .in0_valid(echo_in0_valid)
, .in0_data(echo_in0_data)
, .in1_ready(echo_in1_ready)
, .in1_valid(echo_in1_valid)
, .in1_data(echo_in1_data)
, .out_ready(tx_ready)
, .out_valid(tx_valid)
, .out_data(tx_data)
);
command_parser parser
( .clock(clock)
, .resetn(resetn)
, .uart_ready(rx_ready)
, .uart_valid(rx_valid)
, .uart_data(rx_data)
, .echo_ready(echo_in0_ready)
, .echo_valid(echo_in0_valid)
, .echo_data(echo_in0_data)
, .command_ready(command_ready)
, .command_valid(command_valid)
, .command_address(command_address)
, .command_write(command_write)
, .command_data(command_data)
);
ram_controller ram
( .clock(clock)
, .resetn(resetn)
, .command_ready(command_ready)
, .command_valid(command_valid)
, .command_address(command_address)
, .command_write(command_write)
, .command_data(command_data)
, .result_ready(result_ready)
, .result_valid(result_valid)
, .result_data(result_data)
, .ram_resetn(ram_resetn)
, .ram_csn(ram_csn)
, .ram_clkp(ram_clkp)
, .ram_clkn(ram_clkn)
, .ram_rwds_oe(ram_rwds_oe)
, .ram_rwds_in(ram_rwds)
, .ram_rwds_out(ram_rwds_out)
, .ram_data_oe(ram_data_oe)
, .ram_data_in(ram_data)
, .ram_data_out(ram_data_out)
);
result_printer print
( .clock(clock)
, .resetn(resetn)
, .result_ready(result_ready)
, .result_valid(result_valid)
, .result_data(result_data)
, .echo_ready(echo_in1_ready)
, .echo_valid(echo_in1_valid)
, .echo_data(echo_in1_data)
);
endmodule
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