Initial commit.

11 files changed, 574 insertions, 0 deletions

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..796b96d
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+/build
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..d270ffb
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,37 @@
+VERILOG := $(wildcard **.sv)
+HEADERS := $(wildcard **.svh)
+CPPSRCS := $(wildcard **.cpp)
+COLLATERAL := $(wildcard **.hex)
+
+QUARTUS ?= /opt/quartus-lite/20.1.1.720/
+
+QUARTUS_SH := $(QUARTUS)/quartus/bin/quartus_sh
+
+sim: build/Vtop
+        $<
+.PHONY: sim
+
+gui: build/toycpu.qpf
+        cd build; $(QUARTUS_SH) --gui toycpu
+.PHONY: gui
+
+qpf: build/toycpu.qpf
+.PHONY: qpf
+
+pof: build/toycpu.pof
+.PHONY: pof
+
+build/Vtop: $(VERILOG) $(HEADERS) $(CPPSRCS) $(COLLATERAL)
+        @mkdir -p build
+        verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -O3 --Mdir build --trace --cc --build --exe --top-module top $(VERILOG) $(CPPSRCS)
+
+build/toycpu.pof: build/toycpu.qpf $(VERILOG) $(COLLATERAL)
+        cd build; $(QUARTUS_SH) --flow compile toycpu
+
+build/toycpu.qpf: init.tcl
+        @mkdir -p build
+        cd build; $(QUARTUS_SH) -t ../$< $(addprefix $(PWD),$(VERILOG))
+
+clean:
+        rm -rf build
+.PHONY: clean
diff --git a/bin2bcd.sv b/bin2bcd.sv
new file mode 100644
index 0000000..80dc633
--- /dev/null
+++ b/bin2bcd.sv
@@ -0,0 +1,98 @@
+module bin2bcd
+    #(  BITS = 8
+    ,   BASE = 10
+    )
+    (   input   bit clk
+    ,   input   bit reset
+
+    ,   output  bit             bin_ready
+    ,   input   bit             bin_valid   `define bin_valid $past(bin_valid)
+    ,   input   bit [BITS-1:0]  bin_data    `define bin_data $past(bin_data)
+
+    ,   input   bit                             bcd_ready   `define bcd_ready $past(bcd_ready)
+    ,   output  bit                             bcd_valid
+    ,   output  bit [DIGITS-1:0][BASE_BITS-1:0] bcd_data
+    );
+
+// FIXME I don't think this works for odd bases
+
+localparam BASE_BITS = $clog2(BASE);
+localparam SLACK = (1 << BASE_BITS) - BASE;
+localparam DIGITS = $rtoi($ceil($ln(1 << BITS) / $ln(BASE)));
+localparam CARRY_TEST = $rtoi($ceil($itor(BASE) / 2));
+localparam CARRY_ADD = $rtoi($ceil($itor(SLACK) / 2));
+
+`ifdef DEBUG_BIN2BCD
+
+initial $display("%d BITS", BITS);
+initial $display("%d BASE", BASE);
+initial $display("%d BASE_BITS", BASE_BITS);
+initial $display("%d SLACK", SLACK);
+initial $display("%d DIGITS", DIGITS);
+initial $display("%d CARRY_TEST", CARRY_TEST);
+initial $display("%d CARRY_ADD", CARRY_ADD);
+
+initial for(int i = 0; i < BASE; i = i + 1) begin
+    // verilator lint_off WIDTH
+    automatic bit [BASE_BITS-1:0] n = i;
+    automatic bit [BASE_BITS-1:0] a = n >= CARRY_TEST ? CARRY_ADD : 0;
+    automatic bit [BASE_BITS-1:0] s = n + a;
+    // verilator lint_on WIDTH
+    automatic bit c;
+    automatic bit [BASE_BITS-1:0] d;
+    {c, d} = {s, 1'b0};
+    $display("\t\t(%x + %x => %x) * 2 => %x:%x", n, a, s, c, d);
+end
+
+`endif
+
+bit bin_b_valid;
+bit [BITS-1:0] bin_b_data;
+
+bit [DIGITS-1:0][BASE_BITS-1:0] bcd;;
+
+bit [$clog2(BITS):0] work;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        bin_ready = 0;
+        bcd_valid = 0;
+        bin_b_valid = 0;
+    end else begin
+        if (bin_ready && `bin_valid) begin
+            bin_b_valid = 1;
+            bin_b_data = `bin_data;
+            bcd = 0;
+            work = BITS;
+            for (int i = BITS; i > 0; i = i - 1) begin
+                if (bin_b_data[BITS-1]) break;
+                bin_b_data = { bin_b_data[BITS-2:0], 1'b0 };
+                work = work - 1;
+            end
+        end
+
+        if (bin_b_valid && work != 0) begin
+            for (int i = 0; i < DIGITS; i = i + 1)
+                // verilator lint_off WIDTH
+                if (bcd[i] >= CARRY_TEST) bcd[i] = bcd[i] + CARRY_ADD;
+                // verilator lint_on WIDTH
+            for (int i = DIGITS - 1; i > 0; i = i - 1)
+                bcd[i] = { bcd[i][BASE_BITS-2:0], bcd[i-1][BASE_BITS-1] };
+            bcd[0] = { bcd[0][BASE_BITS-2:0], bin_b_data[BITS-1] };
+            bin_b_data = { bin_b_data[BITS-2:0], 1'b0 };
+
+            work = work - 1;
+        end
+
+        if (`bcd_ready) bcd_valid = 0;
+        if (!bcd_valid && bin_b_valid && work == 0) begin
+            bcd_valid = 1;
+            bcd_data = bcd;
+            bin_b_valid = 0;
+        end
+
+        bin_ready = !bin_b_valid;
+    end
+end
+
+endmodule
diff --git a/fibseq.sv b/fibseq.sv
new file mode 100644
index 0000000..f877b98
--- /dev/null
+++ b/fibseq.sv
@@ -0,0 +1,30 @@
+module fibseq
+    #(  BITS = 8
+    )
+    (   input   bit clk
+    ,   input   bit reset
+
+    ,   input   bit             ready   `define ready $past(ready)
+    ,   output  bit             valid
+    ,   output  bit [BITS-1:0]  data
+    );
+
+bit [BITS-1:0] a;
+bit [BITS-1:0] b;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        valid = 0;
+        a = 0;
+        b = 1;
+    end else begin
+        if (`ready) valid = 0;
+        if (!valid) begin
+            valid = 1;
+            data = a;
+            {a, b} = {b, a + b};
+        end
+    end
+end
+
+endmodule
diff --git a/init.tcl b/init.tcl
new file mode 100644
index 0000000..66cea3f
--- /dev/null
+++ b/init.tcl
@@ -0,0 +1,18 @@
+global quartus
+
+project_new toycpu -revision toycpu -overwrite
+
+set_global_assignment -name DEVICE 10CL025YU256I7G
+
+set_global_assignment -name TOP_LEVEL_ENTITY top
+
+set_location_assignment -to clk PIN_E1
+set_location_assignment -to reset_n PIN_J15
+
+create_base_clock -fmax "50 MHz" -target clk clock_50m
+
+foreach arg $quartus(args) {
+    set_global_assignment -name VERILOG_FILE $arg
+}
+
+project_close
diff --git a/jtag_uart.hex b/jtag_uart.hex
new file mode 100644
index 0000000..504999f
--- /dev/null
+++ b/jtag_uart.hex
@@ -0,0 +1,6 @@
+@0
+
+// "Hello, FPGA!\n"
+48 65 6c 6c 6f 2c 20 46 50 47 41 21 0a
+
+00
diff --git a/jtag_uart.sv b/jtag_uart.sv
new file mode 100644
index 0000000..ddb5ecb
--- /dev/null
+++ b/jtag_uart.sv
@@ -0,0 +1,82 @@
+module jtag_uart
+    #(  INSTANCE = 0
+
+    ,   RX_FIFO_BITS = 6
+    ,   TX_FIFO_BITS = 6
+    )
+    (   input   bit clk
+    ,   input   bit reset
+
+    ,   input   bit         rx_ready    `define rx_ready $past(rx_ready)
+    ,   output  bit         rx_valid
+    ,   output  bit [7:0]   rx_data
+
+    ,   output  bit         tx_ready
+    ,   input   bit         tx_valid    `define tx_valid $past(tx_valid)
+    ,   input   bit [7:0]   tx_data     `define tx_data $past(tx_data)
+    );
+
+`ifdef SYNTHESIS
+
+alt_jtag_atlantic
+    #(  .INSTANCE_ID(INSTANCE)
+    ,   .LOG2_RXFIFO_DEPTH(RX_FIFO_BITS)
+    ,   .LOG2_TXFIFO_DEPTH(TX_FIFO_BITS)
+    ,   .SLD_AUTO_INSTANCE_INDEX("NO")
+    ) real_jtag
+    (   .clk(clk)
+    ,   .rst_n(!reset)
+    ,   .r_dat(tx_data)
+    ,   .r_val(tx_valid)
+    ,   .r_ena(tx_ready)
+    ,   .t_dat(rx_data)
+    ,   .t_dav(rx_ready)
+    ,   .t_ena(rx_valid)
+    );
+
+`else
+
+bit [7:0] sim_rx_rom [0:(1<<16)-1];
+initial $readmemh("jtag_uart.hex", sim_rx_rom);
+
+bit [15:0] sim_rx_addr;
+
+bit tx_b_valid;
+bit [7:0] tx_b_data;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        rx_valid = 0;
+        tx_ready = 0;
+        sim_rx_addr = 0;
+        tx_b_valid = 0;
+    end else begin
+        automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr];
+
+        // RX logic
+        if (`rx_ready) rx_valid = 0;
+        if (!rx_valid && (sim_rx_data != 0)) begin
+`ifdef JTAG_UART_LOCAL_ECHO
+            $write("%s", sim_rx_data);
+`endif
+            rx_valid = 1;
+            rx_data = sim_rx_data;
+            sim_rx_addr = sim_rx_addr + 1;
+        end
+
+        // TX logic
+        if (tx_ready && `tx_valid) begin
+            tx_b_valid = 1;
+            tx_b_data = `tx_data;
+        end
+        if (tx_b_valid) begin
+            $write("%s", tx_b_data);
+            tx_b_valid = 0;
+        end
+        tx_ready = !tx_b_valid;
+    end
+end
+
+`endif
+
+endmodule
diff --git a/main.cpp b/main.cpp
new file mode 100644
index 0000000..3f49cb6
--- /dev/null
+++ b/main.cpp
@@ -0,0 +1,56 @@
+#include <cstdint>
+#include <iostream>
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+
+#include "Vtop.h"
+
+int main(int argc, const char *argv[])
+{
+    Verilated::commandArgs(argc, argv);
+
+    Verilated::traceEverOn(true);
+    VerilatedVcdC vcd;
+
+    Vtop top;
+    top.trace(&vcd, 100 /* levels of hierarchy */);
+
+    vcd.set_time_unit("ns");
+    vcd.set_time_resolution("ns");
+    vcd.open("build/out.vcd");
+
+    std::cout << "*** RESET SEQUENCE ***\n";
+
+    std::uint64_t time = 0;
+
+    top.clk = 0;
+    top.reset_n = 0;
+    top.eval();
+    vcd.dump(++time);
+
+    top.clk = 1;
+    top.eval();
+    vcd.dump(++time);
+
+    top.clk = 0;
+    top.reset_n = 1;
+    top.eval();
+    vcd.dump(++time);
+
+    std::cout << "*** MAIN LOOP ***\n";
+
+    for (unsigned int i = 0; i < 500 && !Verilated::gotFinish(); ++i) {
+        top.clk = 1;
+        top.eval();
+        vcd.dump(++time);
+        top.clk = 0;
+        top.eval();
+        vcd.dump(++time);
+    }
+
+    std::cout << "\n";
+
+    vcd.close();
+
+    return 0;
+}
diff --git a/ntoa.sv b/ntoa.sv
new file mode 100644
index 0000000..c55c9e6
--- /dev/null
+++ b/ntoa.sv
@@ -0,0 +1,83 @@
+module ntoa
+    #(  BITS = 8
+    )
+    (   input   bit clk
+    ,   input   bit reset
+
+    ,   output  bit             n_ready
+    ,   input   bit             n_valid `define n_valid $past(n_valid)
+    ,   input   bit [BITS-1:0]  n_data  `define n_data $past(n_data)
+
+    ,   input   bit         a_ready `define a_ready $past(a_ready)
+    ,   output  bit         a_valid
+    ,   output  bit [7:0]   a_data
+    );
+
+bit bcd_ready;
+bit bcd_valid;
+bit [b2b.DIGITS-1:0][b2b.BASE_BITS-1:0] bcd_data;
+
+bin2bcd
+    #(  .BITS(BITS)
+    ,   .BASE(10)
+    ) b2b
+    (   .clk(clk)
+    ,   .reset(reset)
+
+    ,   .bin_ready(n_ready)
+    ,   .bin_valid(n_valid)
+    ,   .bin_data(n_data)
+
+    ,   .bcd_ready(bcd_ready)
+    ,   .bcd_valid(bcd_valid)   `define bcd_valid $past(bcd_valid)
+    ,   .bcd_data(bcd_data)     `define bcd_data $past(bcd_data)
+    );
+
+bit bcd_b_valid;
+bit [b2b.DIGITS-1:0][b2b.BASE_BITS-1:0] bcd_b_data;
+
+bit [$clog2(b2b.DIGITS):0] work;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        a_valid = 0;
+        bcd_ready = 0;
+        bcd_b_valid = 0;
+    end else begin
+        if (bcd_ready && `bcd_valid) begin
+            bcd_b_valid = 1;
+            bcd_b_data = `bcd_data;
+            // verilator lint_off WIDTH
+            work = b2b.DIGITS;
+            // verilator lint_on WIDTH
+            for (int i = b2b.DIGITS; i > 1; i = i - 1) begin
+                if (bcd_b_data[b2b.DIGITS-1] != 0) break;
+                bcd_b_data = { bcd_b_data[b2b.DIGITS-2:0], {b2b.BASE_BITS{1'b0}} };
+                work = work - 1;
+            end
+        end
+
+        if (`a_ready) a_valid = 0;
+        if (!a_valid && bcd_b_valid) begin
+            if (work != 0) begin
+                a_valid = 1;
+                // verilator lint_off WIDTH
+                if (bcd_b_data[b2b.DIGITS-1] < 10)
+                    a_data = "0" + bcd_b_data[b2b.DIGITS-1];
+                else
+                    a_data = "a" + bcd_b_data[b2b.DIGITS-1] - 10;
+                // verilator lint_off WIDTH
+                bcd_b_data = { bcd_b_data[b2b.DIGITS-2:0], {b2b.BASE_BITS{1'b0}} };
+                work = work - 1;
+            end else begin
+                a_valid = 1;
+                a_data = ",";
+                bcd_b_valid = 0;
+            end
+        end
+
+        bcd_ready = !bcd_b_valid;
+    end
+end
+
+endmodule
diff --git a/rom.hex b/rom.hex
new file mode 100644
index 0000000..ee75917
--- /dev/null
+++ b/rom.hex
@@ -0,0 +1,18 @@
+@0
+
+// "Hello, world!\n"
+48 65 6c 6c 6f 2c 20 77 6f 72 6c 64 21 0a
+
+// "I will now echo your input: "
+49 20 77 69 6c 6c 20 6e 6f 77 20 65 63 68 6f 20
+79 6f 75 72 20 69 6e 70 75 74 3a 20
+
+// At this point, will switch to ECHO mode until it reads a newline.
+00
+
+// "The Fibonacci sequence: "
+54 68 65 20 46 69 62 6f 6e 61 63 63 69 20 73 65
+71 75 65 6e 63 65 3a 20
+
+// At this point, will switch to FIB mode until end of time.
+00
diff --git a/top.sv b/top.sv
new file mode 100644
index 0000000..4acfdeb
--- /dev/null
+++ b/top.sv
@@ -0,0 +1,145 @@
+module top
+    #(  FIB_BITS = 16
+    ,   ROM_BITS = 8
+    )
+    (   input   bit clk     // verilator public
+    ,   input   bit reset_n // verilator public
+    );
+
+bit reset;
+assign reset = !reset_n;
+
+bit [7:0] rom [0:(1<<ROM_BITS)-1];
+initial $readmemh("rom.hex", rom);
+
+bit [ROM_BITS-1:0] addr;
+
+bit rx_ready;
+bit rx_valid;
+bit [7:0] rx_data;
+
+bit tx_ready;
+bit tx_valid;
+bit [7:0] tx_data;
+
+jtag_uart
+    #(  .INSTANCE(0)
+    ) uart0
+    (   .clk(clk)
+    ,   .reset(reset)
+
+    ,   .rx_ready(rx_ready)
+    ,   .rx_valid(rx_valid) `define rx_valid $past(rx_valid)
+    ,   .rx_data(rx_data)   `define rx_data $past(rx_data)
+
+    ,   .tx_ready(tx_ready) `define tx_ready $past(tx_ready)
+    ,   .tx_valid(tx_valid)
+    ,   .tx_data(tx_data)
+    );
+
+bit fib_ready;
+bit fib_valid;
+bit [FIB_BITS-1:0] fib_data;
+
+fibseq
+    #(  .BITS(FIB_BITS)
+    ) fib
+    (   .clk(clk)
+    ,   .reset(reset)
+
+    ,   .ready(fib_ready)
+    ,   .valid(fib_valid)
+    ,   .data(fib_data)
+    );
+
+bit fib_a_ready;
+bit fib_a_valid;
+bit [7:0] fib_a_data;
+
+ntoa
+    #(  .BITS(FIB_BITS)
+    ) fib_ntoa
+    (   .clk(clk)
+    ,   .reset(reset)
+
+    ,   .n_ready(fib_ready)
+    ,   .n_valid(fib_valid)
+    ,   .n_data(fib_data)
+
+    ,   .a_ready(fib_a_ready)
+    ,   .a_valid(fib_a_valid)   `define fib_a_valid $past(fib_a_valid)
+    ,   .a_data(fib_a_data)     `define fib_a_data $past(fib_a_data)
+    );
+
+enum
+    {   INTRO_ECHO
+    ,   ECHO
+    ,   INTRO_FIB
+    ,   FIB
+    } state;
+
+bit tmp_valid;
+bit [7:0] tmp_data;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        addr = 0;
+        rx_ready = 0;
+        tx_valid = 0;
+        fib_a_ready = 0;
+        state = state.first;
+        tmp_valid = 0;
+    end else unique0 case (state)
+
+        INTRO_ECHO, INTRO_FIB: begin
+            automatic bit [7:0] data = rom[addr];
+            if (`tx_ready) tx_valid = 0;
+            if (!tx_valid && (data != 0)) begin
+                tx_valid = 1;
+                tx_data = data;
+                addr = addr + 1;
+            end else if (data == 0) begin
+                addr = addr + 1;
+                state = state.next;
+            end
+        end
+
+        ECHO: begin
+            if (`tx_ready && tx_valid && tx_data == "\n") begin
+                // FIXME race; we aren't going to consume input this cycle, but we might have tmp_valid or rx_ready asserted
+                rx_ready = 0;
+                tx_valid = 0;
+                state = INTRO_FIB;
+            end else begin
+                if (`tx_ready) tx_valid = 0;
+                if (rx_ready && `rx_valid) begin
+                    tmp_valid = 1;
+                    tmp_data = `rx_data;
+                end
+                if (!tx_valid && tmp_valid) begin
+                    tx_valid = 1;
+                    tx_data = tmp_data;
+                    tmp_valid = 0;
+                end
+                rx_ready = !tmp_valid;
+            end
+        end
+
+        FIB: begin
+            if (`tx_ready) tx_valid = 0;
+            if (fib_a_ready && `fib_a_valid) begin
+                tmp_valid = 1;
+                tmp_data = `fib_a_data;
+            end
+            if (!tx_valid && tmp_valid) begin
+                tx_valid = 1;
+                tx_data = tmp_data;
+                tmp_valid = 0;
+            end
+            fib_a_ready = !tmp_valid;
+        end
+
+    endcase
+end
+
+endmodule