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| author | Julian Blake Kongslie | 2021-03-28 14:03:50 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2021-03-28 14:03:50 -0700 |
| commit | 93a4ad185a48e8f2da76cc62fca8160ba4c960a6 (patch) | |
| tree | b8bbd0f85b31fd85bcc8efb961bbc66fc8b11fec /altera/clocks.sdc | |
| parent | Parallel verilator build. (diff) | |
| download | toycpu-93a4ad185a48e8f2da76cc62fca8160ba4c960a6.tar.xz | |
Diffstat (limited to '')
| -rw-r--r-- | altera/clocks.sdc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/altera/clocks.sdc b/altera/clocks.sdc index f613011..239c91a 100644 --- a/altera/clocks.sdc +++ b/altera/clocks.sdc | |||
| @@ -1 +1,3 @@ | |||
| 1 | # This is the clock for timing analysis, not timing-driven synthesis. | ||
| 2 | # See init.tcl for the other clock. | ||
| 1 | create_clock -period "50 MHz" clk | 3 | create_clock -period "50 MHz" clk |