Additional cleanup to make it Quartus-friendly.

1 files changed, 7 insertions, 6 deletions

diff --git a/bin2bcd.sv b/bin2bcd.sv
index 5e2dbd3..9b1609b 100644
--- a/bin2bcd.sv
+++ b/bin2bcd.sv
@@ -1,23 +1,24 @@
+`include "utils.svh"
+
 module bin2bcd
     #(  BITS = 8
     ,   BASE = 10
+    ,   BASE_BITS = $clog2(BASE)
+    ,   DIGITS = 3 // should be ceil[log(2**BITS) base BASE] which is hard to do in Verilog :-(
     ,   MAX_SKIP = BITS
     )
     (   input   bit clk
     ,   input   bit reset
 
     ,   output  bit             bin_ready
-    ,   input   bit             bin_valid   `define bin_valid $past(bin_valid)
-    ,   input   bit [BITS-1:0]  bin_data    `define bin_data $past(bin_data)
+    ,   input   bit             bin_valid   `define bin_valid `past(bin_valid)
+    ,   input   bit [BITS-1:0]  bin_data    `define bin_data `past(bin_data)
 
-    ,   input   bit                             bcd_ready   `define bcd_ready $past(bcd_ready)
+    ,   input   bit                             bcd_ready   `define bcd_ready `past(bcd_ready)
     ,   output  bit                             bcd_valid
     ,   output  bit [DIGITS-1:0][BASE_BITS-1:0] bcd_data
     );
 
-localparam BASE_BITS = $clog2(BASE);
-localparam DIGITS = $rtoi($ceil($ln(1 << BITS) / $ln(BASE)));
-
 bit bin_b_valid;
 bit [BITS-1:0] bin_b_data;