Initial commit.

1 files changed, 18 insertions, 0 deletions

diff --git a/init.tcl b/init.tcl
new file mode 100644
index 0000000..66cea3f
--- /dev/null
+++ b/init.tcl
@@ -0,0 +1,18 @@
+global quartus
+
+project_new toycpu -revision toycpu -overwrite
+
+set_global_assignment -name DEVICE 10CL025YU256I7G
+
+set_global_assignment -name TOP_LEVEL_ENTITY top
+
+set_location_assignment -to clk PIN_E1
+set_location_assignment -to reset_n PIN_J15
+
+create_base_clock -fmax "50 MHz" -target clk clock_50m
+
+foreach arg $quartus(args) {
+    set_global_assignment -name VERILOG_FILE $arg
+}
+
+project_close