Reorganize repo layout to make it a little easier to work within.

1 files changed, 0 insertions, 27 deletions

diff --git a/init.tcl b/init.tcl
deleted file mode 100644
index 4640ea1..0000000
--- a/init.tcl
+++ /dev/null
@@ -1,27 +0,0 @@
-project_new toycpu -revision toycpu -overwrite
-
-set_global_assignment -name DEVICE 10CL025YU256I7G
-
-set_global_assignment -name TOP_LEVEL_ENTITY top
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
-set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
-
-set_location_assignment PIN_E1  -to clk
-set_location_assignment PIN_J15 -to reset_n
-
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset_n
-
-create_base_clock -fmax "50 MHz" clk
-
-set_global_assignment -name CDF_FILE programmer.cdf
-set_global_assignment -name HEX_FILE rom.hex
-set_global_assignment -name SDC_FILE clocks.sdc
-set_global_assignment -name VERILOG_FILE bin2bcd.sv
-set_global_assignment -name VERILOG_FILE fibseq.sv
-set_global_assignment -name VERILOG_FILE jtag_uart.sv
-set_global_assignment -name VERILOG_FILE ntoa.sv
-set_global_assignment -name VERILOG_FILE top.sv
-set_global_assignment -name VERILOG_FILE utils.svh
-
-project_close