Reorganize repo layout to make it a little easier to work within.

1 files changed, 0 insertions, 84 deletions

diff --git a/jtag_uart.sv b/jtag_uart.sv
deleted file mode 100644
index 5c4857d..0000000
--- a/jtag_uart.sv
+++ /dev/null
@@ -1,84 +0,0 @@
-`include "utils.svh"
-
-module jtag_uart
-    #(  INSTANCE = 0
-
-    ,   RX_FIFO_BITS = 6
-    ,   TX_FIFO_BITS = 6
-    )
-    (   input   bit clk
-    ,   input   bit reset
-
-    ,   input   bit         rx_ready    `define rx_ready `past(rx_ready)
-    ,   output  bit         rx_valid
-    ,   output  bit [7:0]   rx_data
-
-    ,   output  bit         tx_ready
-    ,   input   bit         tx_valid    `define tx_valid `past(tx_valid)
-    ,   input   bit [7:0]   tx_data     `define tx_data `past(tx_data)
-    );
-
-`ifdef SYNTHESIS
-
-alt_jtag_atlantic
-    #(  .INSTANCE_ID(INSTANCE)
-    ,   .LOG2_RXFIFO_DEPTH(RX_FIFO_BITS)
-    ,   .LOG2_TXFIFO_DEPTH(TX_FIFO_BITS)
-    ,   .SLD_AUTO_INSTANCE_INDEX("NO")
-    ) real_jtag
-    (   .clk(clk)
-    ,   .rst_n(!reset)
-    ,   .r_dat(tx_data)
-    ,   .r_val(tx_valid)
-    ,   .r_ena(tx_ready)
-    ,   .t_dat(rx_data)
-    ,   .t_dav(rx_ready)
-    ,   .t_ena(rx_valid)
-    );
-
-`else
-
-bit [7:0] sim_rx_rom [0:(1<<16)-1];
-initial $readmemh("jtag_uart.hex", sim_rx_rom);
-
-bit [15:0] sim_rx_addr;
-
-bit tx_b_valid;
-bit [7:0] tx_b_data;
-
-always_ff @(posedge clk) begin
-    if (reset) begin
-        rx_valid = 0;
-        tx_ready = 0;
-        sim_rx_addr = 0;
-        tx_b_valid = 0;
-    end else begin
-        automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr];
-
-        // RX logic
-        if (`rx_ready) rx_valid = 0;
-        if (!rx_valid && (sim_rx_data != 0)) begin
-`ifdef JTAG_UART_LOCAL_ECHO
-            $write("%s", sim_rx_data);
-`endif
-            rx_valid = 1;
-            rx_data = sim_rx_data;
-            sim_rx_addr = sim_rx_addr + 1;
-        end
-
-        // TX logic
-        if (tx_ready && `tx_valid) begin
-            tx_b_valid = 1;
-            tx_b_data = `tx_data;
-        end
-        if (tx_b_valid) begin
-            $write("%s", tx_b_data);
-            tx_b_valid = 0;
-        end
-        tx_ready = !tx_b_valid;
-    end
-end
-
-`endif
-
-endmodule