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| author | Julian Blake Kongslie | 2021-03-28 14:03:50 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2021-03-28 14:03:50 -0700 |
| commit | 93a4ad185a48e8f2da76cc62fca8160ba4c960a6 (patch) | |
| tree | b8bbd0f85b31fd85bcc8efb961bbc66fc8b11fec /tcl | |
| parent | Parallel verilator build. (diff) | |
| download | toycpu-93a4ad185a48e8f2da76cc62fca8160ba4c960a6.tar.xz | |
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/init.tcl | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tcl/init.tcl b/tcl/init.tcl index 6621e6a..689a61c 100644 --- a/tcl/init.tcl +++ b/tcl/init.tcl | |||
| @@ -14,6 +14,8 @@ proc pin {loc net} { | |||
| 14 | pin E1 clk | 14 | pin E1 clk |
| 15 | pin J15 reset_n | 15 | pin J15 reset_n |
| 16 | 16 | ||
| 17 | # This is the clock for timing-driven synthesis, not timing analysis. | ||
| 18 | # See clocks.sdf for the other clock. | ||
| 17 | create_base_clock -fmax "50 MHz" clk | 19 | create_base_clock -fmax "50 MHz" clk |
| 18 | 20 | ||
| 19 | proc add_files {typ ext dir} { | 21 | proc add_files {typ ext dir} { |