Initial commit.

1 files changed, 145 insertions, 0 deletions

diff --git a/top.sv b/top.sv
new file mode 100644
index 0000000..4acfdeb
--- /dev/null
+++ b/top.sv
@@ -0,0 +1,145 @@
+module top
+    #(  FIB_BITS = 16
+    ,   ROM_BITS = 8
+    )
+    (   input   bit clk     // verilator public
+    ,   input   bit reset_n // verilator public
+    );
+
+bit reset;
+assign reset = !reset_n;
+
+bit [7:0] rom [0:(1<<ROM_BITS)-1];
+initial $readmemh("rom.hex", rom);
+
+bit [ROM_BITS-1:0] addr;
+
+bit rx_ready;
+bit rx_valid;
+bit [7:0] rx_data;
+
+bit tx_ready;
+bit tx_valid;
+bit [7:0] tx_data;
+
+jtag_uart
+    #(  .INSTANCE(0)
+    ) uart0
+    (   .clk(clk)
+    ,   .reset(reset)
+
+    ,   .rx_ready(rx_ready)
+    ,   .rx_valid(rx_valid) `define rx_valid $past(rx_valid)
+    ,   .rx_data(rx_data)   `define rx_data $past(rx_data)
+
+    ,   .tx_ready(tx_ready) `define tx_ready $past(tx_ready)
+    ,   .tx_valid(tx_valid)
+    ,   .tx_data(tx_data)
+    );
+
+bit fib_ready;
+bit fib_valid;
+bit [FIB_BITS-1:0] fib_data;
+
+fibseq
+    #(  .BITS(FIB_BITS)
+    ) fib
+    (   .clk(clk)
+    ,   .reset(reset)
+
+    ,   .ready(fib_ready)
+    ,   .valid(fib_valid)
+    ,   .data(fib_data)
+    );
+
+bit fib_a_ready;
+bit fib_a_valid;
+bit [7:0] fib_a_data;
+
+ntoa
+    #(  .BITS(FIB_BITS)
+    ) fib_ntoa
+    (   .clk(clk)
+    ,   .reset(reset)
+
+    ,   .n_ready(fib_ready)
+    ,   .n_valid(fib_valid)
+    ,   .n_data(fib_data)
+
+    ,   .a_ready(fib_a_ready)
+    ,   .a_valid(fib_a_valid)   `define fib_a_valid $past(fib_a_valid)
+    ,   .a_data(fib_a_data)     `define fib_a_data $past(fib_a_data)
+    );
+
+enum
+    {   INTRO_ECHO
+    ,   ECHO
+    ,   INTRO_FIB
+    ,   FIB
+    } state;
+
+bit tmp_valid;
+bit [7:0] tmp_data;
+
+always_ff @(posedge clk) begin
+    if (reset) begin
+        addr = 0;
+        rx_ready = 0;
+        tx_valid = 0;
+        fib_a_ready = 0;
+        state = state.first;
+        tmp_valid = 0;
+    end else unique0 case (state)
+
+        INTRO_ECHO, INTRO_FIB: begin
+            automatic bit [7:0] data = rom[addr];
+            if (`tx_ready) tx_valid = 0;
+            if (!tx_valid && (data != 0)) begin
+                tx_valid = 1;
+                tx_data = data;
+                addr = addr + 1;
+            end else if (data == 0) begin
+                addr = addr + 1;
+                state = state.next;
+            end
+        end
+
+        ECHO: begin
+            if (`tx_ready && tx_valid && tx_data == "\n") begin
+                // FIXME race; we aren't going to consume input this cycle, but we might have tmp_valid or rx_ready asserted
+                rx_ready = 0;
+                tx_valid = 0;
+                state = INTRO_FIB;
+            end else begin
+                if (`tx_ready) tx_valid = 0;
+                if (rx_ready && `rx_valid) begin
+                    tmp_valid = 1;
+                    tmp_data = `rx_data;
+                end
+                if (!tx_valid && tmp_valid) begin
+                    tx_valid = 1;
+                    tx_data = tmp_data;
+                    tmp_valid = 0;
+                end
+                rx_ready = !tmp_valid;
+            end
+        end
+
+        FIB: begin
+            if (`tx_ready) tx_valid = 0;
+            if (fib_a_ready && `fib_a_valid) begin
+                tmp_valid = 1;
+                tmp_data = `fib_a_data;
+            end
+            if (!tx_valid && tmp_valid) begin
+                tx_valid = 1;
+                tx_data = tmp_data;
+                tmp_valid = 0;
+            end
+            fib_a_ready = !tmp_valid;
+        end
+
+    endcase
+end
+
+endmodule