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authorJulian Blake Kongslie2021-03-23 21:52:41 -0700
committerJulian Blake Kongslie2021-03-23 21:54:44 -0700
commit8056863ce3e95db52e027a0f0babe51df1cb9a4e (patch)
treed35ce72f92e8a9b6f1dce49572a49b3117c5827e /top.sv
parentAdding olamic hook to autobuild source archives. (diff)
downloadtoycpu-8056863ce3e95db52e027a0f0babe51df1cb9a4e.tar.xz
Additional cleanup to make it Quartus-friendly.
Diffstat (limited to 'top.sv')
-rw-r--r--top.sv17
1 files changed, 11 insertions, 6 deletions
diff --git a/top.sv b/top.sv
index cbb5b55..0244020 100644
--- a/top.sv
+++ b/top.sv
@@ -1,6 +1,10 @@
1`include "utils.svh"
2
1module top 3module top
2 #( FIB_BITS = 16 4 #( FIB_BITS = 16
3 , FIB_BASE = 10 5 , FIB_BASE = 10
6 , FIB_DIGITS = 5
7
4 , ROM_BITS = 8 8 , ROM_BITS = 8
5 ) 9 )
6 ( input bit clk // verilator public 10 ( input bit clk // verilator public
@@ -30,10 +34,10 @@ jtag_uart
30 , .reset(reset) 34 , .reset(reset)
31 35
32 , .rx_ready(rx_ready) 36 , .rx_ready(rx_ready)
33 , .rx_valid(rx_valid) `define rx_valid $past(rx_valid) 37 , .rx_valid(rx_valid) `define rx_valid `past(rx_valid)
34 , .rx_data(rx_data) `define rx_data $past(rx_data) 38 , .rx_data(rx_data) `define rx_data `past(rx_data)
35 39
36 , .tx_ready(tx_ready) `define tx_ready $past(tx_ready) 40 , .tx_ready(tx_ready) `define tx_ready `past(tx_ready)
37 , .tx_valid(tx_valid) 41 , .tx_valid(tx_valid)
38 , .tx_data(tx_data) 42 , .tx_data(tx_data)
39 ); 43 );
@@ -60,6 +64,7 @@ bit [7:0] fib_a_data;
60ntoa 64ntoa
61 #( .BITS(FIB_BITS) 65 #( .BITS(FIB_BITS)
62 , .BASE(FIB_BASE) 66 , .BASE(FIB_BASE)
67 , .DIGITS(FIB_DIGITS)
63 ) fib_ntoa 68 ) fib_ntoa
64 ( .clk(clk) 69 ( .clk(clk)
65 , .reset(reset) 70 , .reset(reset)
@@ -69,8 +74,8 @@ ntoa
69 , .n_data(fib_data) 74 , .n_data(fib_data)
70 75
71 , .a_ready(fib_a_ready) 76 , .a_ready(fib_a_ready)
72 , .a_valid(fib_a_valid) `define fib_a_valid $past(fib_a_valid) 77 , .a_valid(fib_a_valid) `define fib_a_valid `past(fib_a_valid)
73 , .a_data(fib_a_data) `define fib_a_data $past(fib_a_data) 78 , .a_data(fib_a_data) `define fib_a_data `past(fib_a_data)
74 ); 79 );
75 80
76enum 81enum
@@ -91,7 +96,7 @@ always_ff @(posedge clk) begin
91 fib_a_ready = 0; 96 fib_a_ready = 0;
92 state = state.first; 97 state = state.first;
93 tmp_valid = 0; 98 tmp_valid = 0;
94 end else unique0 case (state) 99 end else case (state)
95 100
96 INTRO_ECHO, INTRO_FIB: begin 101 INTRO_ECHO, INTRO_FIB: begin
97 automatic bit [7:0] data = rom[addr]; 102 automatic bit [7:0] data = rom[addr];