1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
|
module bin2bcd
#( BITS = 8
, BASE = 10
, MAX_SKIP = BITS
)
( input bit clk
, input bit reset
, output bit bin_ready
, input bit bin_valid `define bin_valid $past(bin_valid)
, input bit [BITS-1:0] bin_data `define bin_data $past(bin_data)
, input bit bcd_ready `define bcd_ready $past(bcd_ready)
, output bit bcd_valid
, output bit [DIGITS-1:0][BASE_BITS-1:0] bcd_data
);
localparam BASE_BITS = $clog2(BASE);
localparam DIGITS = $rtoi($ceil($ln(1 << BITS) / $ln(BASE)));
bit bin_b_valid;
bit [BITS-1:0] bin_b_data;
bit [DIGITS-1:0][BASE_BITS-1:0] bcd;;
bit [$clog2(BITS):0] work;
always_ff @(posedge clk) begin
if (reset) begin
bin_ready = 0;
bcd_valid = 0;
bin_b_valid = 0;
end else begin
if (bin_ready && `bin_valid) begin
bin_b_valid = 1;
bin_b_data = `bin_data;
bcd = 0;
work = BITS;
for (int i = 0; i < BITS && i < MAX_SKIP; ++i) begin
if (bin_b_data[BITS-1]) break;
bin_b_data = { bin_b_data[BITS-2:0], 1'b0 };
work = work - 1;
end
end
if (bin_b_valid && work != 0) begin
automatic bit carry = bin_b_data[BITS-1];
for (int i = 0; i < DIGITS; ++i) begin
{carry, bcd[i]} = {bcd[i], carry};
if ({carry, bcd[i]} >= BASE) begin
// verilator lint_off WIDTH
bcd[i] = {carry, bcd[i]} - BASE;
// verilator lint_on WIDTH
carry = 1;
end
end
assert(!carry);
bin_b_data = bin_b_data << 1;
work = work - 1;
end
if (`bcd_ready) bcd_valid = 0;
if (!bcd_valid && bin_b_valid && work == 0) begin
bcd_valid = 1;
bcd_data = bcd;
bin_b_valid = 0;
end
bin_ready = !bin_b_valid;
end
end
endmodule
|
