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project_new toycpu -revision toycpu -overwrite
set_global_assignment -name DEVICE 10CL025YU256I7G
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
proc pin {loc net} {
set_location_assignment -to $net "PIN_$loc"
set_instance_assignment -name IO_STANDARD "3.3V LVTTL" -to $net
}
pin E1 clk
pin J15 reset_n
# This is the clock for timing-driven synthesis, not timing analysis.
# See clocks.sdf for the other clock.
create_base_clock -fmax "50 MHz" clk
proc add_files {typ ext dir} {
foreach name [glob -nocomplain -directory $dir -type f "*.$ext"] {
set_global_assignment -name "${typ}_FILE" $name
}
}
proc add_dir {dir} {
add_files CDF cdf $dir
add_files HEX hex $dir
add_files SDC sdc $dir
add_files VERILOG sv $dir
add_files VERILOG svh $dir
foreach subdir [glob -nocomplain -directory $dir -type d *] {
add_dir $subdir
}
}
add_dir .
project_close
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