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authorJulian Blake Kongslie2023-01-22 14:27:27 -0800
committerJulian Blake Kongslie2023-01-22 14:27:27 -0800
commit58da72b83d4f6ef1a729ef5fafc9cb64331af601 (patch)
tree6f321bc34e4bfea3d2dc7ebd343acdeb4f9e5e25 /uarch/core.h
parentAdd deadman timer (only ten cycles!) based on time between interruptable points. (diff)
downloadbiggolf-58da72b83d4f6ef1a729ef5fafc9cb64331af601.tar.xz
Fix focal 69.
(by accident, by adding a d-side cache with write-through stores, and propagating writes to the i-side cache)
Diffstat (limited to 'uarch/core.h')
-rw-r--r--uarch/core.h19
1 files changed, 10 insertions, 9 deletions
diff --git a/uarch/core.h b/uarch/core.h
index ebfd388..a4ad0fe 100644
--- a/uarch/core.h
+++ b/uarch/core.h
@@ -38,8 +38,6 @@ struct inst_bundle {
38struct fetch_stage : public infra::sim { 38struct fetch_stage : public infra::sim {
39 core &c; 39 core &c;
40 40
41 memory::inline_cache<8, 2> cache;
42
43 unsigned int pc; 41 unsigned int pc;
44 42
45 bool didrestart = false; 43 bool didrestart = false;
@@ -99,6 +97,10 @@ struct core {
99 iomodel &system; 97 iomodel &system;
100 funcchecker checker; 98 funcchecker checker;
101 99
100 // <SETS_LOG2, WAYS>
101 memory::inline_cache<8, 2> icache;
102 memory::inline_cache<8, 2> dcache;
103
102 std::optional<restart> restarto; 104 std::optional<restart> restarto;
103 unsigned int gen = 0; 105 unsigned int gen = 0;
104 106
@@ -113,8 +115,6 @@ struct core {
113 infra::port<memory::dram::response> fetch_mem_responsep; 115 infra::port<memory::dram::response> fetch_mem_responsep;
114 infra::port<fetch_bundle> fetch_bundlep; 116 infra::port<fetch_bundle> fetch_bundlep;
115 117
116 infra::port<memory::dram::command> decode_mem_commandp;
117 infra::port<memory::dram::response> decode_mem_responsep;
118 infra::port<inst_bundle> decode_to_exec_instp; 118 infra::port<inst_bundle> decode_to_exec_instp;
119 119
120 infra::port<inst_bundle> indir_instp; 120 infra::port<inst_bundle> indir_instp;
@@ -123,7 +123,8 @@ struct core {
123 infra::port<memory::dram::response> indir_mem_responsep; 123 infra::port<memory::dram::response> indir_mem_responsep;
124 infra::port<inst_bundle> indir_to_exec_instp; 124 infra::port<inst_bundle> indir_to_exec_instp;
125 125
126 infra::port<memory::dram::command> exec_mem_commandp; 126 infra::port<memory::dram::command> exec_mem_load_commandp;
127 infra::port<memory::dram::command> exec_mem_store_commandp;
127 infra::port<memory::dram::response> exec_mem_responsep; 128 infra::port<memory::dram::response> exec_mem_responsep;
128 129
129 // Global counters (should be Gray code in FPGA implementation, only do == comparisons) 130 // Global counters (should be Gray code in FPGA implementation, only do == comparisons)
@@ -142,10 +143,10 @@ struct core {
142 { 143 {
143 mem.commandp = &mem_commandp; 144 mem.commandp = &mem_commandp;
144 mem_command_arb.outp = &mem_commandp; 145 mem_command_arb.outp = &mem_commandp;
145 mem_command_arb.peerp[0] = &exec_mem_commandp; 146 mem_command_arb.peerp[0] = &exec_mem_store_commandp;
146 mem_command_arb.peerp[1] = &indir_mem_store_commandp; 147 mem_command_arb.peerp[1] = &exec_mem_load_commandp;
147 mem_command_arb.peerp[2] = &indir_mem_load_commandp; 148 mem_command_arb.peerp[2] = &indir_mem_store_commandp;
148 mem_command_arb.peerp[3] = &decode_mem_commandp; 149 mem_command_arb.peerp[3] = &indir_mem_load_commandp;
149 mem_command_arb.peerp[4] = &fetch_mem_commandp; 150 mem_command_arb.peerp[4] = &fetch_mem_commandp;
150 } 151 }
151}; 152};