summaryrefslogtreecommitdiff
path: root/sim/counter.sv
diff options
context:
space:
mode:
authorJulian Blake Kongslie2021-07-16 13:22:51 -0700
committerJulian Blake Kongslie2021-07-16 13:22:51 -0700
commit765420c81d144bb08021a7aa09a9a0692f5d6322 (patch)
tree757bee21385f646fe1fedb1eeba627acbb8cdd09 /sim/counter.sv
parentReformat modules.rb to be a little easier to read. (diff)
downloadbreadboarding-765420c81d144bb08021a7aa09a9a0692f5d6322.tar.xz
Add counter module and simplify board design for shift instructions.
Diffstat (limited to '')
-rw-r--r--sim/counter.sv38
1 files changed, 38 insertions, 0 deletions
diff --git a/sim/counter.sv b/sim/counter.sv
new file mode 100644
index 0000000..1316783
--- /dev/null
+++ b/sim/counter.sv
@@ -0,0 +1,38 @@
1module counter
2 #( parameter UROM = "<no file specified>"
3 , parameter UIP_BITS = 15
4 , parameter UROM_BITS = 8
5 , parameter BUS_BITS = 16
6 )
7 ( input bit clk
8 , input bit reset
9 , input bit [UIP_BITS-1:0] uip
10 , inout bit [BUS_BITS-1:0] abus
11 , inout bit [BUS_BITS-1:0] dbus
12 );
13
14bit [BUS_BITS-1:0] x;
15
16typedef enum
17 { LOAD
18 , INCREMENT
19 , DECREMENT
20 , OUTDATA
21 } CtrlBit;
22
23bit [UROM_BITS-1:0] ctrl;
24urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);
25
26assign dbus = ctrl[OUTDATA] ? x : {(BUS_BITS){1'bZ}};
27
28always @(posedge clk) begin
29 if (ctrl[LOAD]) begin
30 x <= dbus;
31 end else if (ctrl[INCREMENT]) begin
32 x <= x + 1;
33 end else if (ctrl[DECREMENT]) begin
34 x <= x - 1;
35 end
36end
37
38endmodule