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authorJulian Blake Kongslie2021-07-06 09:44:36 -0700
committerJulian Blake Kongslie2021-07-06 09:44:36 -0700
commit60e1775b874015a3451e4bde10a8eb30701b1165 (patch)
tree477a2835c0f7e616bdeeabe6aee85f8af8b79650 /sim/pc.sv
downloadbreadboarding-60e1775b874015a3451e4bde10a8eb30701b1165.tar.xz
Initial commit.
Diffstat (limited to '')
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1 files changed, 36 insertions, 0 deletions
diff --git a/sim/pc.sv b/sim/pc.sv
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1module pc
2 #( parameter UROM = "<no file specified>"
3 , parameter UIP_BITS = 15
4 , parameter UROM_BITS = 8
5 , parameter BUS_BITS = 16
6 , parameter RESET = 0
7 )
8 ( input bit clk
9 , input bit reset
10 , input bit [UIP_BITS-1:0] uip
11 , inout bit [BUS_BITS-1:0] abus
12 , inout bit [BUS_BITS-1:0] dbus
13 );
14
15bit [BUS_BITS-1:0] addr;
16
17typedef enum
18 { LOAD
19 , INCREMENT
20 , OUTADDR
21 } CtrlBit;
22
23bit [UROM_BITS-1:0] ctrl;
24urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);
25
26assign abus = ctrl[OUTADDR] ? addr : {(BUS_BITS){1'bZ}};
27
28always @(posedge clk) begin
29 if (reset) begin
30 addr <= RESET;
31 end else begin
32 addr <= (ctrl[LOAD] ? abus : addr) + (ctrl[INCREMENT] ? 1 : 0);
33 end
34end
35
36endmodule