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-rw-r--r--insts.rb65
-rw-r--r--modules.rb65
-rw-r--r--sim/alu.sv4
-rw-r--r--sim/control.sv3
-rw-r--r--sim/counter.sv38
-rw-r--r--sim/top.sv1
6 files changed, 140 insertions, 36 deletions
diff --git a/insts.rb b/insts.rb
index bc9c156..d24a31d 100644
--- a/insts.rb
+++ b/insts.rb
@@ -105,8 +105,69 @@ alu :xor
105alu :add 105alu :add
106alu :sub 106alu :sub
107alu :cmp 107alu :cmp
108alu :lshift 108
109alu :rshift 109inst "lshift $ #" do
110 uop { @decode.outdata_b; @counter.load; @control.set_uip_if_zero; constaddr($eom) }
111 uop { @decode.outaddr_a; @rf.outdata; @tmp0.loaddata }
112 uop { @tmp0.outdata; @alu.xor; constaddr(0) }
113 shiftloop = uip()
114 uop { @counter.decrement; @alu.outdata; @alu.lshift; constaddr(0) }
115 uop { @counter.outdata; @control.set_uip_if_nonzero; constaddr(shiftloop) }
116 uop { @decode.outaddr_a; @alu.outdata; @rf.store }
117end
118
119inst "lshift $ $" do
120 uop { @decode.outaddr_b; @rf.outdata; @tmp0.loaddata }
121 uop { @tmp0.outdata; @counter.load; @control.set_uip_if_zero; constaddr($eom) }
122 uop { @decode.outaddr_a; @rf.outdata; @tmp0.loaddata }
123 uop { @tmp0.outdata; @alu.xor; constaddr(0) }
124 shiftloop = uip()
125 uop { @counter.decrement; @alu.outdata; @alu.lshift; constaddr(0) }
126 uop { @counter.outdata; @control.set_uip_if_nonzero; constaddr(shiftloop) }
127 uop { @decode.outaddr_a; @alu.outdata; @rf.store }
128end
129
130inst "rshift $ #" do
131 uop { @decode.outdata_b; @counter.load; @control.set_uip_if_zero; constaddr($eom) }
132 uop { @decode.outaddr_a; @rf.outdata; @tmp0.loaddata }
133 uop { @tmp0.outdata; @alu.xor; constaddr(0) }
134 shiftloop = uip()
135 uop { @counter.decrement; @alu.outdata; @alu.rshift; constaddr(0) }
136 uop { @counter.outdata; @control.set_uip_if_nonzero; constaddr(shiftloop) }
137 uop { @decode.outaddr_a; @alu.outdata; @rf.store }
138end
139
140inst "rshift $ $" do
141 uop { @decode.outaddr_b; @rf.outdata; @tmp0.loaddata }
142 uop { @tmp0.outdata; @counter.load; @control.set_uip_if_zero; constaddr($eom) }
143 uop { @decode.outaddr_a; @rf.outdata; @tmp0.loaddata }
144 uop { @tmp0.outdata; @alu.xor; constaddr(0) }
145 shiftloop = uip()
146 uop { @counter.decrement; @alu.outdata; @alu.rshift; constaddr(0) }
147 uop { @counter.outdata; @control.set_uip_if_nonzero; constaddr(shiftloop) }
148 uop { @decode.outaddr_a; @alu.outdata; @rf.store }
149end
150
151inst "rshiftsign $ #" do
152 uop { @decode.outdata_b; @counter.load; @control.set_uip_if_zero; constaddr($eom) }
153 uop { @decode.outaddr_a; @rf.outdata; @tmp0.loaddata }
154 uop { @tmp0.outdata; @alu.xor; constaddr(0) }
155 shiftloop = uip()
156 uop { @tmp0.outaddr; @counter.decrement; @alu.outdata; @alu.rshift }
157 uop { @counter.outdata; @control.set_uip_if_nonzero; constaddr(shiftloop) }
158 uop { @decode.outaddr_a; @alu.outdata; @rf.store }
159end
160
161inst "rshiftsign $ $" do
162 uop { @decode.outaddr_b; @rf.outdata; @tmp0.loaddata }
163 uop { @tmp0.outdata; @counter.load; @control.set_uip_if_zero; constaddr($eom) }
164 uop { @decode.outaddr_a; @rf.outdata; @tmp0.loaddata }
165 uop { @tmp0.outdata; @alu.xor; constaddr(0) }
166 shiftloop = uip()
167 uop { @tmp0.outaddr; @counter.decrement; @alu.outdata; @alu.rshift }
168 uop { @counter.outdata; @control.set_uip_if_nonzero; constaddr(shiftloop) }
169 uop { @decode.outaddr_a; @alu.outdata; @rf.store }
170end
110 171
111def cmpbit(name, bit) 172def cmpbit(name, bit)
112 inst "#{name} $ #" do 173 inst "#{name} $ #" do
diff --git a/modules.rb b/modules.rb
index 752413e..83bfdbd 100644
--- a/modules.rb
+++ b/modules.rb
@@ -1,39 +1,42 @@
1urom :alu, :op, :op_sel0, :op_sel1, :op_sel2, :outaddr, :outdata 1urom :alu, :op, :op_sel0, :op_sel1, :op_sel2, :outaddr, :outdata
2urom_alias :alu, :and, :op 2urom_alias :alu, :and, :op
3urom_alias :alu, :or, :op, :op_sel0 3urom_alias :alu, :or, :op, :op_sel0
4urom_alias :alu, :xor, :op, :op_sel1 4urom_alias :alu, :xor, :op, :op_sel1
5urom_alias :alu, :add, :op, :op_sel0, :op_sel1 5urom_alias :alu, :add, :op, :op_sel0, :op_sel1
6urom_alias :alu, :sub, :op, :op_sel2 6urom_alias :alu, :sub, :op, :op_sel2
7urom_alias :alu, :cmp, :op, :op_sel0, :op_sel2 7urom_alias :alu, :cmp, :op, :op_sel0, :op_sel2
8urom_alias :alu, :lshift, :op, :op_sel1, :op_sel2 8urom_alias :alu, :lshift, :op, :op_sel1, :op_sel2
9urom_alias :alu, :rshift, :op, :op_sel0, :op_sel1, :op_sel2 9urom_alias :alu, :rshift, :op, :op_sel0, :op_sel1, :op_sel2
10 10
11urom :control, :halt, :set_uip_cond, :nocond, :outaddr, :outdata 11urom :control, :halt, :set_uip_cond, :nocond, :icond, :outaddr, :outdata
12urom_alias :control, :set_uip, :set_uip_cond, :nocond 12urom_alias :control, :set_uip, :set_uip_cond, :nocond
13urom_alias :control, :set_uip_if_nonzero, :set_uip_cond 13urom_alias :control, :set_uip_if_nonzero, :set_uip_cond
14urom_alias :control, :set_uip_if_zero, :set_uip_cond, :icond
14 15
15urom :decode, :clear, :decode, :outaddr, :outaddr_sel0, :outaddr_sel1, :outdata, :outdata_sel0, :outdata_sel1 16urom :counter, :load, :increment, :decrement, :outdata
16urom_alias :decode, :outaddr_a, :outaddr
17urom_alias :decode, :outaddr_b, :outaddr, :outaddr_sel0
18urom_alias :decode, :outaddr_uip, :outaddr, :outaddr_sel1
19urom_alias :decode, :outdata_a, :outdata
20urom_alias :decode, :outdata_b, :outdata, :outdata_sel0
21urom_alias :decode, :outdata_needmore, :outdata, :outdata_sel1
22 17
23urom :memory, :store, :outdata 18urom :decode, :clear, :decode, :outaddr, :outaddr_sel0, :outaddr_sel1, :outdata, :outdata_sel0, :outdata_sel1
19urom_alias :decode, :outaddr_a, :outaddr
20urom_alias :decode, :outaddr_b, :outaddr, :outaddr_sel0
21urom_alias :decode, :outaddr_uip, :outaddr, :outaddr_sel1
22urom_alias :decode, :outdata_a, :outdata
23urom_alias :decode, :outdata_b, :outdata, :outdata_sel0
24urom_alias :decode, :outdata_needmore, :outdata, :outdata_sel1
24 25
25urom :pc, :load, :increment, :outaddr 26urom :memory, :store, :outdata
26 27
27urom :rf, :store, :reset, :outdata 28urom :pc, :load, :increment, :outaddr
28 29
29urom :tmp0, :load, :load_sel0, :outaddr, :outdata 30urom :rf, :store, :reset, :outdata
30urom_alias :tmp0, :loaddata, :load
31urom_alias :tmp0, :loadaddr, :load, :load_sel0
32 31
33urom :tmp1, :load, :load_sel0, :outaddr, :outdata 32urom :tmp0, :load, :load_sel0, :outaddr, :outdata
34urom_alias :tmp1, :loaddata, :load 33urom_alias :tmp0, :loaddata, :load
35urom_alias :tmp1, :loadaddr, :load, :load_sel0 34urom_alias :tmp0, :loadaddr, :load, :load_sel0
36 35
37urom :uart, :tx, :rx, :outdata, :outdata_sel0 36urom :tmp1, :load, :load_sel0, :outaddr, :outdata
38urom_alias :uart, :outdata_txfull, :outdata 37urom_alias :tmp1, :loaddata, :load
39urom_alias :uart, :outdata_rxempty, :outdata, :outdata_sel0 38urom_alias :tmp1, :loadaddr, :load, :load_sel0
39
40urom :uart, :tx, :rx, :outdata, :outdata_sel0
41urom_alias :uart, :outdata_txfull, :outdata
42urom_alias :uart, :outdata_rxempty, :outdata, :outdata_sel0
diff --git a/sim/alu.sv b/sim/alu.sv
index 407b083..5583492 100644
--- a/sim/alu.sv
+++ b/sim/alu.sv
@@ -49,8 +49,8 @@ assign cmp_result = {{(BUS_BITS-6){1'b0}},
49 abus > dbus, 49 abus > dbus,
50 abus == dbus, 50 abus == dbus,
51 abus < dbus}; 51 abus < dbus};
52assign lshift_result = (dbus >= BUS_BITS) ? 0 : (abus << dbus); 52assign lshift_result = {dbus[BUS_BITS-2:0], abus[0]};
53assign rshift_result = (dbus >= BUS_BITS) ? 0 : (abus >> dbus); 53assign rshift_result = {abus[BUS_BITS-1], dbus[BUS_BITS-1:1]};
54 54
55bit [BUS_BITS-1:0] newx; 55bit [BUS_BITS-1:0] newx;
56assign newx = 56assign newx =
diff --git a/sim/control.sv b/sim/control.sv
index 7808f61..ddd6401 100644
--- a/sim/control.sv
+++ b/sim/control.sv
@@ -18,6 +18,7 @@ typedef enum
18 { HALT 18 { HALT
19 , SET_UIP_COND 19 , SET_UIP_COND
20 , NOCOND 20 , NOCOND
21 , ICOND
21 , OUTADDR 22 , OUTADDR
22 , OUTDATA 23 , OUTDATA
23 } CtrlBit; 24 } CtrlBit;
@@ -33,7 +34,7 @@ assign abus = ctrl[OUTADDR] ? constant : {(BUS_BITS){1'bZ}};
33assign dbus = ctrl[OUTDATA] ? constant : {(BUS_BITS){1'bZ}}; 34assign dbus = ctrl[OUTDATA] ? constant : {(BUS_BITS){1'bZ}};
34 35
35bit cond; 36bit cond;
36assign cond = (dbus != 0) || ctrl[NOCOND]; 37assign cond = ((dbus != 0) || ctrl[NOCOND]) ^ ctrl[ICOND];
37 38
38always @(posedge clk) begin 39always @(posedge clk) begin
39 if (reset) begin 40 if (reset) begin
diff --git a/sim/counter.sv b/sim/counter.sv
new file mode 100644
index 0000000..1316783
--- /dev/null
+++ b/sim/counter.sv
@@ -0,0 +1,38 @@
1module counter
2 #( parameter UROM = "<no file specified>"
3 , parameter UIP_BITS = 15
4 , parameter UROM_BITS = 8
5 , parameter BUS_BITS = 16
6 )
7 ( input bit clk
8 , input bit reset
9 , input bit [UIP_BITS-1:0] uip
10 , inout bit [BUS_BITS-1:0] abus
11 , inout bit [BUS_BITS-1:0] dbus
12 );
13
14bit [BUS_BITS-1:0] x;
15
16typedef enum
17 { LOAD
18 , INCREMENT
19 , DECREMENT
20 , OUTDATA
21 } CtrlBit;
22
23bit [UROM_BITS-1:0] ctrl;
24urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);
25
26assign dbus = ctrl[OUTDATA] ? x : {(BUS_BITS){1'bZ}};
27
28always @(posedge clk) begin
29 if (ctrl[LOAD]) begin
30 x <= dbus;
31 end else if (ctrl[INCREMENT]) begin
32 x <= x + 1;
33 end else if (ctrl[DECREMENT]) begin
34 x <= x - 1;
35 end
36end
37
38endmodule
diff --git a/sim/top.sv b/sim/top.sv
index 6773739..464b93d 100644
--- a/sim/top.sv
+++ b/sim/top.sv
@@ -14,6 +14,7 @@ bit [BUS_BITS-1:0] dbus;
14 14
15alu #("../out/alu.bin", UIP_BITS, UROM_BITS, BUS_BITS) alu(clk, reset, uip, abus, dbus); 15alu #("../out/alu.bin", UIP_BITS, UROM_BITS, BUS_BITS) alu(clk, reset, uip, abus, dbus);
16control #("../out/control.bin", UIP_BITS, UROM_BITS, BUS_BITS, "../out/consts.0.bin", "../out/consts.1.bin", 'h7ff8) control(clk, reset, uip, abus, dbus); 16control #("../out/control.bin", UIP_BITS, UROM_BITS, BUS_BITS, "../out/consts.0.bin", "../out/consts.1.bin", 'h7ff8) control(clk, reset, uip, abus, dbus);
17counter #("../out/counter.bin", UIP_BITS, UROM_BITS, BUS_BITS) counter(clk, reset, uip, abus, dbus);
17decode #("../out/decode.bin", UIP_BITS, UROM_BITS, BUS_BITS, 12) decode(clk, reset, uip, abus, dbus); 18decode #("../out/decode.bin", UIP_BITS, UROM_BITS, BUS_BITS, 12) decode(clk, reset, uip, abus, dbus);
18memory #("../out/memory.bin", UIP_BITS, UROM_BITS, BUS_BITS, "../out/image.hex", MEM_BITS) memory(clk, reset, uip, abus, dbus); 19memory #("../out/memory.bin", UIP_BITS, UROM_BITS, BUS_BITS, "../out/image.hex", MEM_BITS) memory(clk, reset, uip, abus, dbus);
19pc #("../out/pc.bin", UIP_BITS, UROM_BITS, BUS_BITS, 0) pc(clk, reset, uip, abus, dbus); 20pc #("../out/pc.bin", UIP_BITS, UROM_BITS, BUS_BITS, 0) pc(clk, reset, uip, abus, dbus);
generated by cgit v1.2.3 (git 2.51.0) at 2026-04-18 17:05:41 -0700