Writeback cache using explicit altsyncram instead of inferred memory.HEADmain

1 files changed, 2 insertions, 0 deletions

diff --git a/hdl/mem_broadcast.sv b/hdl/mem_broadcast.sv
index 599be28..e86873e 100644
--- a/hdl/mem_broadcast.sv
+++ b/hdl/mem_broadcast.sv
@@ -48,6 +48,8 @@ module mem_broadcast
                     if (!pdp_valid[ram_data.tag-1]) begin
                         pdp_valid[ram_data.tag-1] = 1;
                         pdp_data[ram_data.tag-1].address = hold_data.address[`PDP_ADDRESS_BITS-1:$clog2(`RAM_LINE_WORDS)];
+                        pdp_data[ram_data.tag-1].snoop = 0;
+                        pdp_data[ram_data.tag-1].data_valid = 1;
                         pdp_data[ram_data.tag-1].data = hold_data.data;
                         hold_valid = 0;
                     end