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| author | Julian Blake Kongslie | 2022-03-18 08:59:41 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-03-18 08:59:41 -0700 |
| commit | 08a154de3bc7df73115a860a35db2173abfde9a3 (patch) | |
| tree | cfcdbafef947789daa72fbc2e89d1b4d015b22fc /hdl | |
| parent | Ignore colons on inputs; use them to separate words in output. (diff) | |
| download | multipdp8-08a154de3bc7df73115a860a35db2173abfde9a3.tar.xz | |
Minor paranoia about ensuring that we're in the correct half_state
coming out of t_rwr delay between memory transactions
Diffstat (limited to 'hdl')
| -rw-r--r-- | hdl/ram_controller.sv | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv index 8922a09..14a1609 100644 --- a/hdl/ram_controller.sv +++ b/hdl/ram_controller.sv | |||
| @@ -129,6 +129,7 @@ module ram_controller | |||
| 129 | ram_data_oe = 0; | 129 | ram_data_oe = 0; |
| 130 | ram_csn = 1; | 130 | ram_csn = 1; |
| 131 | ram_clkp = 0; | 131 | ram_clkp = 0; |
| 132 | half_state = half_state.first; | ||
| 132 | if (trwr_counter != 0) --trwr_counter; | 133 | if (trwr_counter != 0) --trwr_counter; |
| 133 | end else if (half_state == TOGGLE_CLOCK) begin | 134 | end else if (half_state == TOGGLE_CLOCK) begin |
| 134 | half_state = half_state.next; | 135 | half_state = half_state.next; |