Add a clock output pin for debugging the PLL.

1 files changed, 3 insertions, 0 deletions

diff --git a/hdl/top.sv b/hdl/top.sv
index 38ab638..dcf04b5 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -7,6 +7,7 @@ module top
     ,   inout   wire    [10:1]  gpioa
     ,   inout   wire    [28:13] gpiob
     ,   inout   wire    [40:31] gpioc
+    ,   output  wire            clock_out
 
     ,   output  bit             ram_resetn
     ,   output  bit             ram_csn
@@ -28,6 +29,8 @@ module top
         ,   .reset(internal_reset)
         );
 
+    assign clock_out = internal_clock;
+
     bit         ram_rx_ready;
     bit         ram_rx_valid;
     uart_byte_t ram_rx_data;