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* Writeback cache using explicit altsyncram instead of inferred memory.HEADmainJulian Blake Kongslie2022-07-241-4/+2
* Rename memory message types for more clarity.Julian Blake Kongslie2022-07-101-8/+8
* Add cache clearing to the command parser.Julian Blake Kongslie2022-06-051-0/+6
* Working L1 cache.Julian Blake Kongslie2022-06-051-6/+45
* Add support for bulk memory dumping to command parser.Julian Blake Kongslie2022-05-291-0/+12
* Change to 1Mbaud RS232Julian Blake Kongslie2022-05-151-1/+1
* Only phase shift the RS232 tx clock when we are between bytes.Julian Blake Kongslie2022-05-151-0/+5
* Consistent RS232 wire names (DCE side names is used everywhere)Julian Blake Kongslie2022-05-151-10/+10
* Make the calculation for OVERSAMPLE more explicit.Julian Blake Kongslie2022-05-081-1/+1
* *Proper* serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.Julian Blake Kongslie2022-05-081-61/+57
* Oversample RS232 RX uart.Julian Blake Kongslie2022-04-221-12/+28
* Working (but very slow) RS232 UARTJulian Blake Kongslie2022-04-171-1/+132
* Use the DF and IF switches as a selector for which PDP-8 owns the panel.Julian Blake Kongslie2022-03-271-89/+92
* Add a clock output pin for debugging the PLL.Julian Blake Kongslie2022-03-271-0/+3
* Reduce internal clock speed to 30MHz.Julian Blake Kongslie2022-03-271-2/+2
* Run ~*EIGHT GODDAMN PDP-8s IN PARALLEL*~Julian Blake Kongslie2022-03-201-41/+113
* Add memory arbiter and broadcast in between command UART and DRAM.Julian Blake Kongslie2022-03-131-17/+63
* Change FIFO size for UARTs to 1024 bytes in each direction.Julian Blake Kongslie2022-03-131-2/+2
* Initial commit.Julian Blake Kongslie2022-02-271-0/+298
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