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authorJulian Blake Kongslie2021-11-21 13:28:55 -0800
committerJulian Blake Kongslie2021-11-21 13:28:55 -0800
commita9a3b8f7ab7f2067843a9a642447a9b7270440ce (patch)
treefc7a5ba3dd7c5c0f5d77593c18a58f7fa376f2b5 /hdl/core.sv
parentImplement single-stepping the core. (diff)
downloadnoncpu-a9a3b8f7ab7f2067843a9a642447a9b7270440ce.tar.xz
Implement switches Start and LoadAdd.
Diffstat (limited to 'hdl/core.sv')
-rw-r--r--hdl/core.sv56
1 files changed, 53 insertions, 3 deletions
diff --git a/hdl/core.sv b/hdl/core.sv
index 43a4a1a..14660f5 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -7,6 +7,13 @@ module core
7 ( input bit clk 7 ( input bit clk
8 , input bit reset 8 , input bit reset
9 9
10 , input bit [2:0] switch_df
11 , input bit [2:0] switch_if
12 , input bit [ADDR_BITS-1:0] switch_sr
13 , input bit switch_start
14 , input bit switch_load_add
15 , input bit switch_dep
16 , input bit switch_exam
10 , input bit switch_cont 17 , input bit switch_cont
11 , input bit switch_stop 18 , input bit switch_stop
12 , input bit switch_sing_step 19 , input bit switch_sing_step
@@ -43,6 +50,10 @@ module core
43 ); 50 );
44 51
45bit run; 52bit run;
53bit switch_start_observed;
54bit switch_load_add_observed;
55bit switch_dep_observed;
56bit switch_exam_observed;
46bit switch_cont_observed; 57bit switch_cont_observed;
47assign led_run = run; 58assign led_run = run;
48 59
@@ -53,8 +64,8 @@ bit [ADDR_BITS-1:0] mem_address;
53bit [DATA_BITS-1:0] mem_write_data; 64bit [DATA_BITS-1:0] mem_write_data;
54assign led_current_address = mem_valid; 65assign led_current_address = mem_valid;
55 66
56assign led_df = 0; 67assign led_df = switch_df; // FIXME actually implement DF and IF
57assign led_if = 0; 68assign led_if = switch_if;
58assign led_memaddr = mem_address; 69assign led_memaddr = mem_address;
59 70
60bit mem_read_valid; 71bit mem_read_valid;
@@ -151,6 +162,10 @@ assign led_pause = state == MEMWAIT || state == HALT;
151always_ff @(posedge clk) begin 162always_ff @(posedge clk) begin
152 if (reset) begin 163 if (reset) begin
153 run = 0; 164 run = 0;
165 switch_start_observed = 0;
166 switch_load_add_observed = 0;
167 switch_dep_observed = 0;
168 switch_exam_observed = 0;
154 switch_cont_observed = 0; 169 switch_cont_observed = 0;
155 mem_valid = 0; 170 mem_valid = 0;
156 rx_ready = 0; 171 rx_ready = 0;
@@ -163,9 +178,44 @@ always_ff @(posedge clk) begin
163 kbd_valid = 0; 178 kbd_valid = 0;
164 state = state.first; 179 state = state.first;
165 end else begin 180 end else begin
166 if (switch_cont && !switch_cont_observed) begin 181 if (switch_start && !switch_start_observed) begin
182 switch_start_observed = 1;
167 run = 1; 183 run = 1;
184 mem_valid = 0;
185 acc = 0;
186 link = 1;
187 state = state.first;
188 end
189
190 if (!switch_start)
191 switch_start_observed = 0;
192
193 if (switch_load_add && !switch_load_add_observed) begin
194 switch_load_add_observed = 1;
195 pc = switch_sr;
196 led_pc = pc;
197 end
198
199 if (!switch_load_add)
200 switch_load_add_observed = 0;
201
202 if (switch_dep && !switch_dep_observed) begin
203 switch_dep_observed = 1;
204 end
205
206 if (!switch_dep)
207 switch_dep_observed = 0;
208
209 if (switch_exam && !switch_exam_observed) begin
210 switch_exam_observed = 1;
211 end
212
213 if (!switch_exam)
214 switch_exam_observed = 0;
215
216 if (switch_cont && !switch_cont_observed) begin
168 switch_cont_observed = 1; 217 switch_cont_observed = 1;
218 run = 1;
169 end 219 end
170 220
171 if (!switch_cont) 221 if (!switch_cont)