noncpu - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Implement DF and IF, and Dep and Exam switches.	Julian Blake Kongslie	2021-12-05	1	-0/+5
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*	Interrupt-driven keyboard input.	Julian Blake Kongslie	2021-11-21	1	-1/+1
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*	Implement switches Start and LoadAdd.	Julian Blake Kongslie	2021-11-21	1	-7/+20
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*	Implement single-stepping the core.	Julian Blake Kongslie	2021-10-31	1	-0/+3
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*	Really simple switch debounce.	Julian Blake Kongslie	2021-10-31	1	-2/+2
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*	More blinkenlights work.	Julian Blake Kongslie	2021-10-24	1	-24/+88
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*	Blinkenlights.	Julian Blake Kongslie	2021-10-24	1	-0/+56
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*	Move the core logic out of the top module.	Julian Blake Kongslie	2021-04-18	1	-219/+1
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*	Change synthesis of PLL wrapper to avoid latch logic.pre-dp-8	Julian Blake Kongslie	2021-04-15	1	-2/+2
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*	Use internal PLL for clock and reset generation.	Julian Blake Kongslie	2021-04-14	1	-6/+14
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*	Add UART receive opbit.	Julian Blake Kongslie	2021-04-07	1	-0/+12
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*	Switch back to $past-based scheduling; my clever idea wasn't clever enough.	Julian Blake Kongslie	2021-04-07	1	-60/+45
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*	Change the null byte from no-op to halt.	Julian Blake Kongslie	2021-04-05	1	-1/+1
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*	Change our simulator timing model to use continuous assignment guards.	Julian Blake Kongslie	2021-04-05	1	-50/+65
\| \| \| \| \| \| \|	Instead of depending on verilator getting $past right, this (ab-)uses the SystemVerilog scheduling model which allows us to get a consistent view of the universe by "isolating" the blocking updates. Easier to code to and seems to be more reliable in verilator.
*	Make PC ADDR-sized rather than DATA-sized for now	Julian Blake Kongslie	2021-04-05	1	-3/+3
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*	Remove some old debug messages.	Julian Blake Kongslie	2021-04-05	1	-11/+1
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*	Remove idx, add indirect jumps, renumber opcodes so NOP=0, add absolute ↵	Julian Blake Kongslie	2021-04-04	1	-31/+34
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*	Add indirect memory operations.	Julian Blake Kongslie	2021-04-04	1	-6/+30
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*	Very fancy improved Fibonacci machine, with HDL convert-to-ASCII functionality	Julian Blake Kongslie	2021-04-04	1	-0/+11
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*	Add a Fibonacci sequence to the end of output (no ASCII conversion yet)	Julian Blake Kongslie	2021-03-29	1	-1/+1
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*	Convert to using $sampled instead of $past, for more uniformity.	Julian Blake Kongslie	2021-03-29	1	-8/+8
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*	Fix WIDTH warnings from verilator.	Julian Blake Kongslie	2021-03-29	1	-5/+8
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*	Possibly slightly less lame.	Julian Blake Kongslie	2021-03-28	1	-10/+10
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*	Yet another lame attempt.	Julian Blake Kongslie	2021-03-28	1	-22/+47
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*	Pessimize JTAG UART somewhat.	Julian Blake Kongslie	2021-03-28	1	-8/+1
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*	Use a separate memory module.	Julian Blake Kongslie	2021-03-28	1	-9/+80
\| \| \| \|	Hopefully this will infer a memory the way we want in Quartus.
*	Some more interesting opcodes.	Julian Blake Kongslie	2021-03-28	1	-8/+23
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*	Initial commit.	Julian Blake Kongslie	2021-03-28	1	-0/+89