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| author | Julian Blake Kongslie | 2022-02-16 12:41:28 -0800 |
|---|---|---|
| committer | Julian Blake Kongslie | 2022-02-16 12:41:28 -0800 |
| commit | 6e39b7c16fbad9ddffc0f4eacd1799ca1b995492 (patch) | |
| tree | e538e4291992276da6a3847b02e20028ab8b30ef /altera/clocks.sdc | |
| download | simple-memory-controller-6e39b7c16fbad9ddffc0f4eacd1799ca1b995492.tar.xz | |
Initial commit.
Diffstat (limited to 'altera/clocks.sdc')
| -rw-r--r-- | altera/clocks.sdc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/altera/clocks.sdc b/altera/clocks.sdc new file mode 100644 index 0000000..c08f897 --- /dev/null +++ b/altera/clocks.sdc | |||
| @@ -0,0 +1,3 @@ | |||
| 1 | # This is the clock for timing analysis, not timing-driven synthesis. | ||
| 2 | # See init.tcl for the other clock. | ||
| 3 | create_clock -period "50 MHz" clock | ||