1 files changed, 193 insertions, 0 deletions
diff --git a/hdl/top.sv b/hdl/top.sv
new file mode 100644
index 0000000..babdc95
--- /dev/null
+++ b/hdl/top.sv
@@ -0,0 +1,193 @@
+module top
+    (   input   bit         clock
+    ,   input   bit         resetn
+    ,   output  bit         ramresetn
+    ,   output  bit [1:0]   ramcsn
+    ,   output  bit         ramclkp
+    ,   output  bit         ramclkn
+    ,   input   bit         ramrwds
+    ,   inout   bit [7:0]   ramdata
+    );
+assign ramresetn    = resetn;
+assign ramclkn      = !ramclkp;
+bit         ram_data_oe;
+bit [7:0]   ram_send_data;
+assign ramdata = ram_data_oe ? ram_send_data : 8'bZ;
+bit         rx_ready;
+bit         rx_valid;
+bit [7:0]   rx_data;
+bit         tx_ready;
+bit         tx_valid;
+bit [7:0]   tx_data;
+alt_jtag_atlantic
+    #(  .INSTANCE_ID(0)
+    ,   .LOG2_RXFIFO_DEPTH(6)
+    ,   .LOG2_TXFIFO_DEPTH(6)
+    ,   .SLD_AUTO_INSTANCE_INDEX("NO")
+    ) jtag
+    (   .clk(clock)
+    ,   .rst_n(resetn)
+    ,   .r_dat(tx_data)
+    ,   .r_val(tx_valid)
+    ,   .r_ena(tx_ready)
+    ,   .t_dat(rx_data)
+    ,   .t_dav(rx_ready)
+    ,   .t_ena(rx_valid)
+    );
+bit         input_byte_valid;
+bit [7:0]   input_byte;
+bit [22:0]  address;
+bit [7:0]   data;
+bit         write;
+bit [47:0]  command;
+enum
+    { UART_READ_ADDRESS_OR_COMMAND
+    , UART_READ_DATA_1
+    , UART_READ_DATA_0
+    , RAM_WAIT_READY
+    , RAM_SEND_COMMAND_5
+    , RAM_SEND_COMMAND_4
+    , RAM_SEND_COMMAND_3
+    , RAM_SEND_COMMAND_2
+    , RAM_SEND_COMMAND_1
+    , RAM_SEND_COMMAND_0
+    , RAM_INIT_WAIT_DATA
+    , RAM_WAIT_DATA
+    , RAM_SENDRECV_DATA
+    , UART_WRITE_DATA_1
+    , UART_WRITE_DATA_0
+    } state;
+always @(posedge clock) begin
+    if (!resetn) begin
+        ramcsn[0] = 1;
+        ramcsn[1] = 1;
+        ramclkp = 0;
+        ram_data_oe = 0;
+        rx_ready = 0;
+        tx_valid = 0;
+        input_byte_valid = 0;
+        address = 0;
+        state = state.first;
+    end else begin
+        if (tx_ready) tx_valid = 0;
+        if (rx_valid && !input_byte_valid && !tx_valid) begin
+            tx_valid = 1;
+            tx_data = rx_data;
+            input_byte_valid = 1;
+            input_byte = rx_data;
+        end
+        case (state)
+        UART_READ_ADDRESS_OR_COMMAND:
+            if (input_byte_valid) begin
+                if (input_byte >= "0" && input_byte <= "9") begin
+                    address = address << 4;
+                    address[3:0] = input_byte - "0";
+                end else if (input_byte >= "a" && input_byte <= "f") begin
+                    address = address << 4;
+                    address[3:0] = input_byte - "a" + 10;
+                end else if (input_byte >= "A" && input_byte <= "F") begin
+                    address = address << 4;
+                    address[3:0] = input_byte - "A" + 10;
+                end else if (input_byte == "?") begin
+                    write = 0;
+                    command = {12'b100000000000, address[22:3], 13'b0, address[2:0]};
+                    address = 0;
+                    data = 0;
+                    state = RAM_SEND_COMMAND_5;
+                end else if (input_byte == "=") begin
+                    write = 1;
+                    command = {12'b000000000000, address[22:3], 13'b0, address[2:0]};
+                    address = 0;
+                    data = 0;
+                    state = UART_READ_DATA_1;
+                end
+                input_byte_valid = 0;
+            end
+        UART_READ_DATA_1, UART_READ_DATA_0:
+            if (input_byte_valid) begin
+                if (input_byte >= "0" && input_byte <= "9") begin
+                    data = data << 4;
+                    data[3:0] = input_byte - "0";
+                    state = state.next;
+                end else if (input_byte >= "a" && input_byte <= "f") begin
+                    data = data << 4;
+                    data[3:0] = input_byte - "a" + 10;
+                    state = state.next;
+                end else if (input_byte >= "A" && input_byte <= "F") begin
+                    data = data << 4;
+                    data[3:0] = input_byte - "A" + 10;
+                    state = state.next;
+                end
+                input_byte_valid = 0;
+            end
+        RAM_WAIT_READY:
+            begin
+                ramcsn[0] = 0;
+                if (ramrwds) state = state.next;
+            end
+        RAM_SEND_COMMAND_5, RAM_SEND_COMMAND_4, RAM_SEND_COMMAND_3, RAM_SEND_COMMAND_2, RAM_SEND_COMMAND_1, RAM_SEND_COMMAND_0:
+            begin
+                ramclkp = ~ramclkp;
+                ram_data_oe = 1;
+                ram_send_data = command[47:40];
+                command = command << 8;
+                state = state.next;
+            end
+        RAM_INIT_WAIT_DATA:
+            begin
+                ramclkp = ~ramclkp;
+                ram_data_oe = 0;
+                state = state.next;
+            end
+        RAM_WAIT_DATA:
+            begin
+                ramclkp = ~ramclkp;
+                if (ramrwds) begin
+                    if (write) begin
+                        ram_data_oe = 1;
+                        ram_send_data = data;
+                    end
+                    state = state.next;
+                end
+            end
+        RAM_SENDRECV_DATA:
+            begin
+                ramclkp = ~ramclkp;
+                ramcsn[0] = 1;
+                ram_data_oe = 0;
+                if (write) begin
+                    state = state.first;
+                end else begin
+                    data = ramdata;
+                    state = UART_WRITE_DATA_1;
+                end
+            end
+        UART_WRITE_DATA_1, UART_WRITE_DATA_0:
+            if (!tx_valid) begin
+                tx_valid = 1;
+                if (data[7:4] < 10) begin
+                    tx_data = data[7:4] + "0";
+                end else begin
+                    tx_data = data[7:4] + "A" - 10;
+                end
+                data = data << 4;
+                state = state.next;
+            end
+        endcase
+        rx_ready = !input_byte_valid && !tx_valid;
+    end
+end
+endmodule

diff --git a/hdl/top.sv b/hdl/top.sv new file mode 100644 index 0000000..babdc95 --- /dev/null +++ b/hdl/top.sv
@@ -0,0 +1,193 @@
	1	module top
	2	( input bit clock
	3	, input bit resetn
	4
	5	, output bit ramresetn
	6	, output bit [1:0] ramcsn
	7	, output bit ramclkp
	8	, output bit ramclkn
	9	, input bit ramrwds
	10	, inout bit [7:0] ramdata
	11	);
	12
	13	assign ramresetn = resetn;
	14	assign ramclkn = !ramclkp;
	15
	16	bit ram_data_oe;
	17	bit [7:0] ram_send_data;
	18
	19	assign ramdata = ram_data_oe ? ram_send_data : 8'bZ;
	20
	21	bit rx_ready;
	22	bit rx_valid;
	23	bit [7:0] rx_data;
	24
	25	bit tx_ready;
	26	bit tx_valid;
	27	bit [7:0] tx_data;
	28
	29	alt_jtag_atlantic
	30	#( .INSTANCE_ID(0)
	31	, .LOG2_RXFIFO_DEPTH(6)
	32	, .LOG2_TXFIFO_DEPTH(6)
	33	, .SLD_AUTO_INSTANCE_INDEX("NO")
	34	) jtag
	35	( .clk(clock)
	36	, .rst_n(resetn)
	37	, .r_dat(tx_data)
	38	, .r_val(tx_valid)
	39	, .r_ena(tx_ready)
	40	, .t_dat(rx_data)
	41	, .t_dav(rx_ready)
	42	, .t_ena(rx_valid)
	43	);
	44
	45	bit input_byte_valid;
	46	bit [7:0] input_byte;
	47
	48	bit [22:0] address;
	49	bit [7:0] data;
	50	bit write;
	51
	52	bit [47:0] command;
	53
	54	enum
	55	{ UART_READ_ADDRESS_OR_COMMAND
	56	, UART_READ_DATA_1
	57	, UART_READ_DATA_0
	58	, RAM_WAIT_READY
	59	, RAM_SEND_COMMAND_5
	60	, RAM_SEND_COMMAND_4
	61	, RAM_SEND_COMMAND_3
	62	, RAM_SEND_COMMAND_2
	63	, RAM_SEND_COMMAND_1
	64	, RAM_SEND_COMMAND_0
	65	, RAM_INIT_WAIT_DATA
	66	, RAM_WAIT_DATA
	67	, RAM_SENDRECV_DATA
	68	, UART_WRITE_DATA_1
	69	, UART_WRITE_DATA_0
	70	} state;
	71
	72	always @(posedge clock) begin
	73	if (!resetn) begin
	74	ramcsn[0] = 1;
	75	ramcsn[1] = 1;
	76	ramclkp = 0;
	77	ram_data_oe = 0;
	78	rx_ready = 0;
	79	tx_valid = 0;
	80	input_byte_valid = 0;
	81	address = 0;
	82	state = state.first;
	83	end else begin
	84	if (tx_ready) tx_valid = 0;
	85	if (rx_valid && !input_byte_valid && !tx_valid) begin
	86	tx_valid = 1;
	87	tx_data = rx_data;
	88	input_byte_valid = 1;
	89	input_byte = rx_data;
	90	end
	91	case (state)
	92	UART_READ_ADDRESS_OR_COMMAND:
	93	if (input_byte_valid) begin
	94	if (input_byte >= "0" && input_byte <= "9") begin
	95	address = address << 4;
	96	address[3:0] = input_byte - "0";
	97	end else if (input_byte >= "a" && input_byte <= "f") begin
	98	address = address << 4;
	99	address[3:0] = input_byte - "a" + 10;
	100	end else if (input_byte >= "A" && input_byte <= "F") begin
	101	address = address << 4;
	102	address[3:0] = input_byte - "A" + 10;
	103	end else if (input_byte == "?") begin
	104	write = 0;
	105	command = {12'b100000000000, address[22:3], 13'b0, address[2:0]};
	106	address = 0;
	107	data = 0;
	108	state = RAM_SEND_COMMAND_5;
	109	end else if (input_byte == "=") begin
	110	write = 1;
	111	command = {12'b000000000000, address[22:3], 13'b0, address[2:0]};
	112	address = 0;
	113	data = 0;
	114	state = UART_READ_DATA_1;
	115	end
	116	input_byte_valid = 0;
	117	end
	118	UART_READ_DATA_1, UART_READ_DATA_0:
	119	if (input_byte_valid) begin
	120	if (input_byte >= "0" && input_byte <= "9") begin
	121	data = data << 4;
	122	data[3:0] = input_byte - "0";
	123	state = state.next;
	124	end else if (input_byte >= "a" && input_byte <= "f") begin
	125	data = data << 4;
	126	data[3:0] = input_byte - "a" + 10;
	127	state = state.next;
	128	end else if (input_byte >= "A" && input_byte <= "F") begin
	129	data = data << 4;
	130	data[3:0] = input_byte - "A" + 10;
	131	state = state.next;
	132	end
	133	input_byte_valid = 0;
	134	end
	135	RAM_WAIT_READY:
	136	begin
	137	ramcsn[0] = 0;
	138	if (ramrwds) state = state.next;
	139	end
	140	RAM_SEND_COMMAND_5, RAM_SEND_COMMAND_4, RAM_SEND_COMMAND_3, RAM_SEND_COMMAND_2, RAM_SEND_COMMAND_1, RAM_SEND_COMMAND_0:
	141	begin
	142	ramclkp = ~ramclkp;
	143	ram_data_oe = 1;
	144	ram_send_data = command[47:40];
	145	command = command << 8;
	146	state = state.next;
	147	end
	148	RAM_INIT_WAIT_DATA:
	149	begin
	150	ramclkp = ~ramclkp;
	151	ram_data_oe = 0;
	152	state = state.next;
	153	end
	154	RAM_WAIT_DATA:
	155	begin
	156	ramclkp = ~ramclkp;
	157	if (ramrwds) begin
	158	if (write) begin
	159	ram_data_oe = 1;
	160	ram_send_data = data;
	161	end
	162	state = state.next;
	163	end
	164	end
	165	RAM_SENDRECV_DATA:
	166	begin
	167	ramclkp = ~ramclkp;
	168	ramcsn[0] = 1;
	169	ram_data_oe = 0;
	170	if (write) begin
	171	state = state.first;
	172	end else begin
	173	data = ramdata;
	174	state = UART_WRITE_DATA_1;
	175	end
	176	end
	177	UART_WRITE_DATA_1, UART_WRITE_DATA_0:
	178	if (!tx_valid) begin
	179	tx_valid = 1;
	180	if (data[7:4] < 10) begin
	181	tx_data = data[7:4] + "0";
	182	end else begin
	183	tx_data = data[7:4] + "A" - 10;
	184	end
	185	data = data << 4;
	186	state = state.next;
	187	end
	188	endcase
	189	rx_ready = !input_byte_valid && !tx_valid;
	190	end
	191	end
	192
	193	endmodule