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module top
( input bit clock
, input bit resetn
, output bit ramresetn
, output bit [1:0] ramcsn
, output bit ramclkp
, output bit ramclkn
, input bit ramrwds
, inout bit [7:0] ramdata
);
assign ramresetn = resetn;
assign ramclkn = !ramclkp;
bit ram_data_oe;
bit [7:0] ram_send_data;
assign ramdata = ram_data_oe ? ram_send_data : 8'bZ;
bit rx_ready;
bit rx_valid;
bit [7:0] rx_data;
bit tx_ready;
bit tx_valid;
bit [7:0] tx_data;
alt_jtag_atlantic
#( .INSTANCE_ID(0)
, .LOG2_RXFIFO_DEPTH(6)
, .LOG2_TXFIFO_DEPTH(6)
, .SLD_AUTO_INSTANCE_INDEX("NO")
) jtag
( .clk(clock)
, .rst_n(resetn)
, .r_dat(tx_data)
, .r_val(tx_valid)
, .r_ena(tx_ready)
, .t_dat(rx_data)
, .t_dav(rx_ready)
, .t_ena(rx_valid)
);
bit input_byte_valid;
bit [7:0] input_byte;
bit [22:0] address;
bit [7:0] data;
bit write;
bit [47:0] command;
enum
{ UART_READ_ADDRESS_OR_COMMAND
, UART_READ_DATA_1
, UART_READ_DATA_0
, RAM_WAIT_READY
, RAM_SEND_COMMAND_5
, RAM_SEND_COMMAND_4
, RAM_SEND_COMMAND_3
, RAM_SEND_COMMAND_2
, RAM_SEND_COMMAND_1
, RAM_SEND_COMMAND_0
, RAM_INIT_WAIT_DATA
, RAM_WAIT_DATA
, RAM_SENDRECV_DATA
, UART_WRITE_DATA_1
, UART_WRITE_DATA_0
} state;
always @(posedge clock) begin
if (!resetn) begin
ramcsn[0] = 1;
ramcsn[1] = 1;
ramclkp = 0;
ram_data_oe = 0;
rx_ready = 0;
tx_valid = 0;
input_byte_valid = 0;
address = 0;
state = state.first;
end else begin
if (tx_ready) tx_valid = 0;
if (rx_valid && !input_byte_valid && !tx_valid) begin
tx_valid = 1;
tx_data = rx_data;
input_byte_valid = 1;
input_byte = rx_data;
end
case (state)
UART_READ_ADDRESS_OR_COMMAND:
if (input_byte_valid) begin
if (input_byte >= "0" && input_byte <= "9") begin
address = address << 4;
address[3:0] = input_byte - "0";
end else if (input_byte >= "a" && input_byte <= "f") begin
address = address << 4;
address[3:0] = input_byte - "a" + 10;
end else if (input_byte >= "A" && input_byte <= "F") begin
address = address << 4;
address[3:0] = input_byte - "A" + 10;
end else if (input_byte == "?") begin
write = 0;
command = {12'b100000000000, address[22:3], 13'b0, address[2:0]};
address = 0;
data = 0;
state = RAM_SEND_COMMAND_5;
end else if (input_byte == "=") begin
write = 1;
command = {12'b000000000000, address[22:3], 13'b0, address[2:0]};
address = 0;
data = 0;
state = UART_READ_DATA_1;
end
input_byte_valid = 0;
end
UART_READ_DATA_1, UART_READ_DATA_0:
if (input_byte_valid) begin
if (input_byte >= "0" && input_byte <= "9") begin
data = data << 4;
data[3:0] = input_byte - "0";
state = state.next;
end else if (input_byte >= "a" && input_byte <= "f") begin
data = data << 4;
data[3:0] = input_byte - "a" + 10;
state = state.next;
end else if (input_byte >= "A" && input_byte <= "F") begin
data = data << 4;
data[3:0] = input_byte - "A" + 10;
state = state.next;
end
input_byte_valid = 0;
end
RAM_WAIT_READY:
begin
ramcsn[0] = 0;
if (ramrwds) state = state.next;
end
RAM_SEND_COMMAND_5, RAM_SEND_COMMAND_4, RAM_SEND_COMMAND_3, RAM_SEND_COMMAND_2, RAM_SEND_COMMAND_1, RAM_SEND_COMMAND_0:
begin
ramclkp = ~ramclkp;
ram_data_oe = 1;
ram_send_data = command[47:40];
command = command << 8;
state = state.next;
end
RAM_INIT_WAIT_DATA:
begin
ramclkp = ~ramclkp;
ram_data_oe = 0;
state = state.next;
end
RAM_WAIT_DATA:
begin
ramclkp = ~ramclkp;
if (ramrwds) begin
if (write) begin
ram_data_oe = 1;
ram_send_data = data;
end
state = state.next;
end
end
RAM_SENDRECV_DATA:
begin
ramclkp = ~ramclkp;
ramcsn[0] = 1;
ram_data_oe = 0;
if (write) begin
state = state.first;
end else begin
data = ramdata;
state = UART_WRITE_DATA_1;
end
end
UART_WRITE_DATA_1, UART_WRITE_DATA_0:
if (!tx_valid) begin
tx_valid = 1;
if (data[7:4] < 10) begin
tx_data = data[7:4] + "0";
end else begin
tx_data = data[7:4] + "A" - 10;
end
data = data << 4;
state = state.next;
end
endcase
rx_ready = !input_byte_valid && !tx_valid;
end
end
endmodule
|
