Trivial changes from actually testing at Ducky office.HEADmain

4 files changed, 10 insertions, 5 deletions

diff --git a/altera/clocks.sdc b/altera/clocks.sdc
index f613011..239c91a 100644
--- a/altera/clocks.sdc
+++ b/altera/clocks.sdc
@@ -1 +1,3 @@
+# This is the clock for timing analysis, not timing-driven synthesis.
+# See init.tcl for the other clock.
 create_clock -period "50 MHz" clk
diff --git a/altera/jtag.cdf b/altera/jtag.cdf
index cbe240b..ac80090 100644
--- a/altera/jtag.cdf
+++ b/altera/jtag.cdf
@@ -1,10 +1,9 @@
-/* XXX Copy this from a working setup on Ducky hardware */
 JedecChain;
     FileRevision(JESD32A);
     DefaultMfr(6E);
 
-    P ActionCode(Cfg)
-        Device PartName(10CL025YU256) Path("C:/Users/mike/Desktop/toycpu/") File("toycpu.pof") MfrSpec(OpMask(1));
+    P ActionCode(Ign)
+        Device PartName(10CL025Y) MfrSpec(OpMask(0));
 
 ChainEnd;
 
diff --git a/hdl/top.sv b/hdl/top.sv
index c2f56bc..41b3e23 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -11,8 +11,10 @@ module top
     ,   input   bit reset_n // verilator public
     );
 
-bit reset;
-assign reset = !reset_n;
+bit reset = 0;
+bit have_reset = 0;
+always_ff @(posedge clk) if (reset) have_reset <= 1;
+assign reset = !reset_n || !have_reset;
 
 bit [7:0] rom [0:(1<<ROM_BITS)-1];
 initial $readmemh("mem/rom.hex", rom);
diff --git a/tcl/init.tcl b/tcl/init.tcl
index 6621e6a..689a61c 100644
--- a/tcl/init.tcl
+++ b/tcl/init.tcl
@@ -14,6 +14,8 @@ proc pin {loc net} {
 pin E1  clk
 pin J15 reset_n
 
+# This is the clock for timing-driven synthesis, not timing analysis.
+# See clocks.sdf for the other clock.
 create_base_clock -fmax "50 MHz" clk
 
 proc add_files {typ ext dir} {