7 files changed, 41 insertions, 36 deletions

diff --git a/Makefile b/Makefile
index 9eff3ef..f532ce2 100644
--- a/Makefile
+++ b/Makefile
@@ -1,38 +1,15 @@
-VERILOG := $(wildcard **.sv)
-HEADERS := $(wildcard **.svh)
-CPPSRCS := $(wildcard **.cpp)
-COLLATERAL := $(wildcard **.hex)
+SOURCES := $(wildcard **.sv **.cpp)
+COLLATERAL := $(wildcard **.hex **.svh)
 
 OPTS ?=
 
-QUARTUS ?= /opt/quartus-lite/20.1.1.720/
-
-QUARTUS_SH := $(QUARTUS)/quartus/bin/quartus_sh
-
 sim: build/Vtop
         $<
 .PHONY: sim
 
-gui: build/toycpu.qpf
-        cd build; $(QUARTUS_SH) --gui toycpu
-.PHONY: gui
-
-qpf: build/toycpu.qpf
-.PHONY: qpf
-
-pof: build/toycpu.pof
-.PHONY: pof
-
-build/Vtop: $(VERILOG) $(HEADERS) $(CPPSRCS) $(COLLATERAL)
-        @mkdir -p build
-        verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -O3 $(OPTS) --Mdir build --trace --cc --build --exe --top-module top $(VERILOG) $(CPPSRCS)
-
-build/toycpu.pof: build/toycpu.qpf $(VERILOG) $(COLLATERAL)
-        cd build; $(QUARTUS_SH) --flow compile toycpu
-
-build/toycpu.qpf: init.tcl
+build/Vtop: $(SOURCES) $(COLLATERAL)
         @mkdir -p build
-        cd build; $(QUARTUS_SH) -t ../$< $(addprefix $(PWD),$(VERILOG))
+        verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -O3 $(OPTS) --Mdir build --trace --cc --build --exe --top-module top $(SOURCES)
 
 clean:
         rm -rf build
diff --git a/bin2bcd.sv b/bin2bcd.sv
index 8e618c6..5e2dbd3 100644
--- a/bin2bcd.sv
+++ b/bin2bcd.sv
@@ -21,7 +21,7 @@ localparam DIGITS = $rtoi($ceil($ln(1 << BITS) / $ln(BASE)));
 bit bin_b_valid;
 bit [BITS-1:0] bin_b_data;
 
-bit [DIGITS-1:0][BASE_BITS-1:0] bcd;;
+bit [DIGITS-1:0][BASE_BITS-1:0] bcd;
 
 bit [$clog2(BITS):0] work;
 
diff --git a/build.bat b/build.bat
new file mode 100644
index 0000000..730d487
--- /dev/null
+++ b/build.bat
@@ -0,0 +1,3 @@
+init.bat
+
+quartus_sh.exe --flow compile toycpu
diff --git a/clocks.sdc b/clocks.sdc
new file mode 100644
index 0000000..f613011
--- /dev/null
+++ b/clocks.sdc
@@ -0,0 +1 @@
+create_clock -period "50 MHz" clk
diff --git a/init.bat b/init.bat
new file mode 100644
index 0000000..20ea117
--- /dev/null
+++ b/init.bat
@@ -0,0 +1,3 @@
+if not exist toycpu.qpf {
+    quartus_sh.exe -t init.tcl
+}
diff --git a/init.tcl b/init.tcl
index 66cea3f..33897e5 100644
--- a/init.tcl
+++ b/init.tcl
@@ -1,18 +1,26 @@
-global quartus
-
 project_new toycpu -revision toycpu -overwrite
 
 set_global_assignment -name DEVICE 10CL025YU256I7G
 
 set_global_assignment -name TOP_LEVEL_ENTITY top
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_MACRO "SYNTHESIS=1"
+
+set_location_assignment PIN_E1  -to clk
+set_location_assignment PIN_J15 -to reset_n
 
-set_location_assignment -to clk PIN_E1
-set_location_assignment -to reset_n PIN_J15
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset_n
 
-create_base_clock -fmax "50 MHz" -target clk clock_50m
+create_base_clock -fmax "50 MHz" clk
 
-foreach arg $quartus(args) {
-    set_global_assignment -name VERILOG_FILE $arg
-}
+set_global_assignment -name CDF_FILE programmer.cdf
+set_global_assignment -name HEX_FILE rom.hex
+set_global_assignment -name SDC_FILE clocks.sdc
+set_global_assignment -name VERILOG_FILE bin2bcd.sv
+set_global_assignment -name VERILOG_FILE fibseq.sv
+set_global_assignment -name VERILOG_FILE jtag_uart.sv
+set_global_assignment -name VERILOG_FILE ntoa.sv
+set_global_assignment -name VERILOG_FILE top.sv
 
 project_close
diff --git a/programmer.cdf b/programmer.cdf
new file mode 100644
index 0000000..cbe240b
--- /dev/null
+++ b/programmer.cdf
@@ -0,0 +1,13 @@
+/* XXX Copy this from a working setup on Ducky hardware */
+JedecChain;
+    FileRevision(JESD32A);
+    DefaultMfr(6E);
+
+    P ActionCode(Cfg)
+        Device PartName(10CL025YU256) Path("C:/Users/mike/Desktop/toycpu/") File("toycpu.pof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+    ChainType(JTAG);
+AlteraEnd;