Add counter module and simplify board design for shift instructions.

4 files changed, 43 insertions, 3 deletions

diff --git a/sim/alu.sv b/sim/alu.sv
index 407b083..5583492 100644
--- a/sim/alu.sv
+++ b/sim/alu.sv
@@ -49,8 +49,8 @@ assign cmp_result = {{(BUS_BITS-6){1'b0}},
     abus > dbus,
     abus == dbus,
     abus < dbus};
-assign lshift_result = (dbus >= BUS_BITS) ? 0 : (abus << dbus);
-assign rshift_result = (dbus >= BUS_BITS) ? 0 : (abus >> dbus);
+assign lshift_result = {dbus[BUS_BITS-2:0], abus[0]};
+assign rshift_result = {abus[BUS_BITS-1], dbus[BUS_BITS-1:1]};
 
 bit [BUS_BITS-1:0] newx;
 assign newx =
diff --git a/sim/control.sv b/sim/control.sv
index 7808f61..ddd6401 100644
--- a/sim/control.sv
+++ b/sim/control.sv
@@ -18,6 +18,7 @@ typedef enum
     { HALT
     , SET_UIP_COND
     , NOCOND
+    , ICOND
     , OUTADDR
     , OUTDATA
     } CtrlBit;
@@ -33,7 +34,7 @@ assign abus = ctrl[OUTADDR] ? constant : {(BUS_BITS){1'bZ}};
 assign dbus = ctrl[OUTDATA] ? constant : {(BUS_BITS){1'bZ}};
 
 bit cond;
-assign cond = (dbus != 0) || ctrl[NOCOND];
+assign cond = ((dbus != 0) || ctrl[NOCOND]) ^ ctrl[ICOND];
 
 always @(posedge clk) begin
     if (reset) begin
diff --git a/sim/counter.sv b/sim/counter.sv
new file mode 100644
index 0000000..1316783
--- /dev/null
+++ b/sim/counter.sv
@@ -0,0 +1,38 @@
+module counter
+    #(  parameter   UROM        = "<no file specified>"
+    ,   parameter   UIP_BITS    = 15
+    ,   parameter   UROM_BITS   = 8
+    ,   parameter   BUS_BITS    = 16
+    )
+    (   input   bit                 clk
+    ,   input   bit                 reset
+    ,   input   bit [UIP_BITS-1:0]  uip
+    ,   inout   bit [BUS_BITS-1:0]  abus
+    ,   inout   bit [BUS_BITS-1:0]  dbus
+    );
+
+bit [BUS_BITS-1:0] x;
+
+typedef enum
+    { LOAD
+    , INCREMENT
+    , DECREMENT
+    , OUTDATA
+    } CtrlBit;
+
+bit [UROM_BITS-1:0] ctrl;
+urom#(UROM, UIP_BITS, UROM_BITS) urom(uip, ctrl);
+
+assign dbus = ctrl[OUTDATA] ? x : {(BUS_BITS){1'bZ}};
+
+always @(posedge clk) begin
+    if (ctrl[LOAD]) begin
+        x <= dbus;
+    end else if (ctrl[INCREMENT]) begin
+        x <= x + 1;
+    end else if (ctrl[DECREMENT]) begin
+        x <= x - 1;
+    end
+end
+
+endmodule
diff --git a/sim/top.sv b/sim/top.sv
index 6773739..464b93d 100644
--- a/sim/top.sv
+++ b/sim/top.sv
@@ -14,6 +14,7 @@ bit [BUS_BITS-1:0] dbus;
 
 alu     #("../out/alu.bin",     UIP_BITS, UROM_BITS, BUS_BITS) alu(clk, reset, uip, abus, dbus);
 control #("../out/control.bin", UIP_BITS, UROM_BITS, BUS_BITS, "../out/consts.0.bin", "../out/consts.1.bin", 'h7ff8) control(clk, reset, uip, abus, dbus);
+counter #("../out/counter.bin", UIP_BITS, UROM_BITS, BUS_BITS) counter(clk, reset, uip, abus, dbus);
 decode  #("../out/decode.bin",  UIP_BITS, UROM_BITS, BUS_BITS, 12) decode(clk, reset, uip, abus, dbus);
 memory  #("../out/memory.bin",  UIP_BITS, UROM_BITS, BUS_BITS, "../out/image.hex", MEM_BITS) memory(clk, reset, uip, abus, dbus);
 pc      #("../out/pc.bin",      UIP_BITS, UROM_BITS, BUS_BITS, 0) pc(clk, reset, uip, abus, dbus);