multipdp8 - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add cache clearing to the command parser.	Julian Blake Kongslie	2022-06-05	4	-6/+25
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*	Working L1 cache.	Julian Blake Kongslie	2022-06-05	6	-11/+158
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*	SMC micro.	Julian Blake Kongslie	2022-06-05	2	-1/+65
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*	Support for downloading PAL programs.	Julian Blake Kongslie	2022-06-05	1	-0/+19
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*	More reliable download script.	Julian Blake Kongslie	2022-06-05	1	-4/+4
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*	More nefarious planning...	Julian Blake Kongslie	2022-05-31	1	-2/+3
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*	Update plan.	Julian Blake Kongslie	2022-05-29	1	-4/+4
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*	Add tool for creating a bunch of simultaneous nios2-terminal sessions.	Julian Blake Kongslie	2022-05-29	1	-0/+35
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*	Add Fibonacci Focal script and a dumped memory image with it already loaded.	Julian Blake Kongslie	2022-05-29	2	-0/+265
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*	Add support for bulk memory dumping to command parser.	Julian Blake Kongslie	2022-05-29	3	-31/+85
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*	Tweak con script to do CRLF translation on received stream.	Julian Blake Kongslie	2022-05-29	2	-12/+27
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*	Add extremely sus speedy-download tool which might have made Mike's FTDI	Julian Blake Kongslie	2022-05-29	1	-0/+19
\| \| \| \|	cable glitch enough to need a power cycle.
*	Move stty setup/teardown to separate script; add hconnect script.	Julian Blake Kongslie	2022-05-29	3	-30/+42
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*	Single-cycle bypass when there is no contention on memory arbiter.	Julian Blake Kongslie	2022-05-29	2	-1/+11
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*	Only run selector logic if we need a new selection next cycle.	Julian Blake Kongslie	2022-05-29	1	-1/+4
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*	Add makefile target for uploading "raw UART" images	Julian Blake Kongslie	2022-05-29	1	-1/+19
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*	More planning.	Julian Blake Kongslie	2022-05-22	1	-0/+1
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*	Update PLAN.	Julian Blake Kongslie	2022-05-22	1	-6/+5
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*	Two-cycle memory arbiter, enabling 16 PDP-8s @ 50MHz.	Julian Blake Kongslie	2022-05-22	2	-14/+12
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*	Only sample RS232 signals once per clock; use a delayed flop internally.	Julian Blake Kongslie	2022-05-22	1	-9/+19
\| \| \| \|	This removes metastability issues on inputs and makes everything work.
*	Update plan.	Julian Blake Kongslie	2022-05-15	1	-10/+6
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*	Significantly wider line size for data downloads.	Julian Blake Kongslie	2022-05-15	1	-1/+1
\| \| \| \|	8.5sec for 16 cores!
*	Fix the RS232 receive state machine 😠💢:mad:	Julian Blake Kongslie	2022-05-15	1	-1/+1
\| \| \| \| \| \| \| \| \|	Our current consensus is that we have a bug which causes the RX state machine to make incomprehensible jumps when the sample counter is more than about 9 bits wide. We haven't completely pinned down the problem; we saw it when running at 1Mbaud with a 7 bit (one extra bit) counter. I hate Verilog and Altera, both exclusively and in combination.
*	Change to 1Mbaud RS232	Julian Blake Kongslie	2022-05-15	2	-2/+2
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*	Only phase shift the RS232 tx clock when we are between bytes.	Julian Blake Kongslie	2022-05-15	2	-1/+22
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*	Consistent RS232 wire names (DCE side names is used everywhere)	Julian Blake Kongslie	2022-05-15	3	-39/+39
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*	Change makefile to unconditionally load memory for 16 PDP-8s	Julian Blake Kongslie	2022-05-15	1	-14/+14
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*	Remove extraneous newline (we still have some other one somewhere)	Julian Blake Kongslie	2022-05-08	1	-1/+1
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*	Make the calculation for OVERSAMPLE more explicit.	Julian Blake Kongslie	2022-05-08	1	-1/+1
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*	Demand that CTS is asserted for multiple symbol periods before transmit.	Julian Blake Kongslie	2022-05-08	1	-1/+8
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*	Proper serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.	Julian Blake Kongslie	2022-05-08	11	-132/+322
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*	Make the script for setting up the TTY actually connect.	Julian Blake Kongslie	2022-04-24	1	-0/+6
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*	Add a quick and dirty script to set expected RS232 terminal settings.	Julian Blake Kongslie	2022-04-22	1	-0/+23
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*	Oversample RS232 RX uart.	Julian Blake Kongslie	2022-04-22	2	-42/+77
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*	Asynchronous reset on RS232 uart.	Julian Blake Kongslie	2022-04-22	1	-2/+2
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*	Transmit and receive an even parity bit in RS232 uart.	Julian Blake Kongslie	2022-04-22	1	-0/+23
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*	Transmit two stop bits to RS232 uart.	Julian Blake Kongslie	2022-04-22	1	-2/+8
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*	Refer to wrap bits instead of previous greycode in FIFO greycode calculation.	Julian Blake Kongslie	2022-04-17	1	-2/+2
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*	Fix whitespace/maxlinesize handling in p8bin2uart.	Julian Blake Kongslie	2022-04-17	1	-8/+7
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*	Working (but very slow) RS232 UART	Julian Blake Kongslie	2022-04-17	5	-35/+165
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*	Integrate wrap bits into grey code for FIFO.	Julian Blake Kongslie	2022-03-28	1	-5/+8
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*	Update PLAN.	Julian Blake Kongslie	2022-03-27	1	-13/+10
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*	12 PDP-8s! :-)	Julian Blake Kongslie	2022-03-27	1	-1/+1
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*	A more-fair memory arbiter that actually works.	Julian Blake Kongslie	2022-03-27	1	-31/+34
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*	Add RX/TX/RTS/CTS pin assignments for future RS232 work.	Julian Blake Kongslie	2022-03-27	1	-0/+5
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*	Use the DF and IF switches as a selector for which PDP-8 owns the panel.	Julian Blake Kongslie	2022-03-27	1	-89/+92
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*	Add a clock output pin for debugging the PLL.	Julian Blake Kongslie	2022-03-27	2	-0/+5
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*	Attempt to make somewhat less error-prone downloads.	Julian Blake Kongslie	2022-03-27	2	-6/+5
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*	Reduce internal clock speed to 30MHz.	Julian Blake Kongslie	2022-03-27	2	-3/+3
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*	Attempt to download for 16 PDP-8s.	Julian Blake Kongslie	2022-03-27	1	-8/+16
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