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authorJulian Blake Kongslie2021-07-16 13:22:51 -0700
committerJulian Blake Kongslie2021-07-16 13:22:51 -0700
commit765420c81d144bb08021a7aa09a9a0692f5d6322 (patch)
tree757bee21385f646fe1fedb1eeba627acbb8cdd09 /sim/alu.sv
parentReformat modules.rb to be a little easier to read. (diff)
downloadbreadboarding-765420c81d144bb08021a7aa09a9a0692f5d6322.tar.xz
Add counter module and simplify board design for shift instructions.
Diffstat (limited to 'sim/alu.sv')
-rw-r--r--sim/alu.sv4
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/alu.sv b/sim/alu.sv
index 407b083..5583492 100644
--- a/sim/alu.sv
+++ b/sim/alu.sv
@@ -49,8 +49,8 @@ assign cmp_result = {{(BUS_BITS-6){1'b0}},
49 abus > dbus, 49 abus > dbus,
50 abus == dbus, 50 abus == dbus,
51 abus < dbus}; 51 abus < dbus};
52assign lshift_result = (dbus >= BUS_BITS) ? 0 : (abus << dbus); 52assign lshift_result = {dbus[BUS_BITS-2:0], abus[0]};
53assign rshift_result = (dbus >= BUS_BITS) ? 0 : (abus >> dbus); 53assign rshift_result = {abus[BUS_BITS-1], dbus[BUS_BITS-1:1]};
54 54
55bit [BUS_BITS-1:0] newx; 55bit [BUS_BITS-1:0] newx;
56assign newx = 56assign newx =