multipdp8 - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Oversample RS232 RX uart.	Julian Blake Kongslie	2022-04-22	2	-42/+77
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*	Asynchronous reset on RS232 uart.	Julian Blake Kongslie	2022-04-22	1	-2/+2
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*	Transmit and receive an even parity bit in RS232 uart.	Julian Blake Kongslie	2022-04-22	1	-0/+23
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*	Transmit two stop bits to RS232 uart.	Julian Blake Kongslie	2022-04-22	1	-2/+8
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*	Refer to wrap bits instead of previous greycode in FIFO greycode calculation.	Julian Blake Kongslie	2022-04-17	1	-2/+2
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*	Working (but very slow) RS232 UART	Julian Blake Kongslie	2022-04-17	4	-31/+161
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*	Integrate wrap bits into grey code for FIFO.	Julian Blake Kongslie	2022-03-28	1	-5/+8
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*	12 PDP-8s! :-)	Julian Blake Kongslie	2022-03-27	1	-1/+1
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*	A more-fair memory arbiter that actually works.	Julian Blake Kongslie	2022-03-27	1	-31/+34
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*	Use the DF and IF switches as a selector for which PDP-8 owns the panel.	Julian Blake Kongslie	2022-03-27	1	-89/+92
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*	Add a clock output pin for debugging the PLL.	Julian Blake Kongslie	2022-03-27	1	-0/+3
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*	Reduce internal clock speed to 30MHz.	Julian Blake Kongslie	2022-03-27	1	-2/+2
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*	Don't use SystemVerilog parametric types because Altera doesn't support them.	Julian Blake Kongslie	2022-03-27	1	-9/+9
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*	First pass at RS232 tx/rx modules.	Julian Blake Kongslie	2022-03-27	1	-0/+131
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*	Add basic clock-domain-crossing FIFO.	Julian Blake Kongslie	2022-03-26	1	-0/+68
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*	Run ~EIGHT GODDAMN PDP-8s IN PARALLEL~	Julian Blake Kongslie	2022-03-20	2	-42/+114
\| \| \| \| \| \|	It looks like we could probably fit 16 on the current FPGA, just about. (doesn't meet timing at 50MHz, should in theory work at 40MHz)
*	Cleanup of PDP-8 core to support arbitrated memory protocol.	Julian Blake Kongslie	2022-03-20	1	-190/+109
\| \| \| \|	No support yet for multiple words per line; otherwise complete.
*	Temporary change to PDP-8 internal memory to match controller protocol	Julian Blake Kongslie	2022-03-20	1	-57/+86
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*	Minor paranoia about ensuring that we're in the correct half_state	Julian Blake Kongslie	2022-03-18	1	-0/+1
\| \| \| \|	coming out of t_rwr delay between memory transactions
*	Ignore colons on inputs; use them to separate words in output.	Julian Blake Kongslie	2022-03-18	2	-7/+19
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*	Trivial change to make it a little easier to understand the mem arbiter.	Julian Blake Kongslie	2022-03-18	1	-1/+1
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*	Change command parser to support bulk download script.	Julian Blake Kongslie	2022-03-13	1	-23/+90
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*	Add memory arbiter and broadcast in between command UART and DRAM.	Julian Blake Kongslie	2022-03-13	3	-17/+203
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*	Fix DRAM timings to avoid back-to-back transactions.	Julian Blake Kongslie	2022-03-13	1	-3/+11
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*	Change FIFO size for UARTs to 1024 bytes in each direction.	Julian Blake Kongslie	2022-03-13	2	-4/+4
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*	Print a newline after memory read result prints.	Julian Blake Kongslie	2022-03-13	1	-26/+32
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*	Adding packed keyword to structs and tweaking tag_t slightly.	Julian Blake Kongslie	2022-03-13	1	-7/+7
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*	Switch back to focal69 instead of broken hello.pal.	Julian Blake Kongslie	2022-03-01	1	-2/+1
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*	Don't use the bottom data bit as the ready signal :-D	Julian Blake Kongslie	2022-02-28	1	-1/+1
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*	Initial commit.	Julian Blake Kongslie	2022-02-27	9	-0/+2033