multipdp8 - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	Use the DF and IF switches as a selector for which PDP-8 owns the panel.	Julian Blake Kongslie	2022-03-27	1	-89/+92
*	Add a clock output pin for debugging the PLL.	Julian Blake Kongslie	2022-03-27	1	-0/+3
*	Reduce internal clock speed to 30MHz.	Julian Blake Kongslie	2022-03-27	1	-2/+2
*	Don't use SystemVerilog parametric types because Altera doesn't support them.	Julian Blake Kongslie	2022-03-27	1	-9/+9
*	First pass at RS232 tx/rx modules.	Julian Blake Kongslie	2022-03-27	1	-0/+131
*	Add basic clock-domain-crossing FIFO.	Julian Blake Kongslie	2022-03-26	1	-0/+68
*	Run ~EIGHT GODDAMN PDP-8s IN PARALLEL~	Julian Blake Kongslie	2022-03-20	2	-42/+114
*	Cleanup of PDP-8 core to support arbitrated memory protocol.	Julian Blake Kongslie	2022-03-20	1	-190/+109
*	Temporary change to PDP-8 internal memory to match controller protocol	Julian Blake Kongslie	2022-03-20	1	-57/+86
*	Minor paranoia about ensuring that we're in the correct half_state	Julian Blake Kongslie	2022-03-18	1	-0/+1
*	Ignore colons on inputs; use them to separate words in output.	Julian Blake Kongslie	2022-03-18	2	-7/+19
*	Trivial change to make it a little easier to understand the mem arbiter.	Julian Blake Kongslie	2022-03-18	1	-1/+1
*	Change command parser to support bulk download script.	Julian Blake Kongslie	2022-03-13	1	-23/+90
*	Add memory arbiter and broadcast in between command UART and DRAM.	Julian Blake Kongslie	2022-03-13	3	-17/+203
*	Fix DRAM timings to avoid back-to-back transactions.	Julian Blake Kongslie	2022-03-13	1	-3/+11
*	Change FIFO size for UARTs to 1024 bytes in each direction.	Julian Blake Kongslie	2022-03-13	2	-4/+4
*	Print a newline after memory read result prints.	Julian Blake Kongslie	2022-03-13	1	-26/+32
*	Adding packed keyword to structs and tweaking tag_t slightly.	Julian Blake Kongslie	2022-03-13	1	-7/+7
*	Switch back to focal69 instead of broken hello.pal.	Julian Blake Kongslie	2022-03-01	1	-2/+1
*	Don't use the bottom data bit as the ready signal :-D	Julian Blake Kongslie	2022-02-28	1	-1/+1
*	Initial commit.	Julian Blake Kongslie	2022-02-27	9	-0/+2033