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* Working L1 cache.Julian Blake Kongslie2022-06-054-9/+156
* Add support for bulk memory dumping to command parser.Julian Blake Kongslie2022-05-293-31/+85
* Single-cycle bypass when there is no contention on memory arbiter.Julian Blake Kongslie2022-05-291-0/+11
* Only run selector logic if we need a new selection next cycle.Julian Blake Kongslie2022-05-291-1/+4
* Two-cycle memory arbiter, enabling 16 PDP-8s @ 50MHz.Julian Blake Kongslie2022-05-222-14/+12
* Only sample RS232 signals once per clock; use a delayed flop internally.Julian Blake Kongslie2022-05-221-9/+19
* Fix the RS232 receive state machine 😠💢:mad:Julian Blake Kongslie2022-05-151-1/+1
* Change to 1Mbaud RS232Julian Blake Kongslie2022-05-151-1/+1
* Only phase shift the RS232 tx clock when we are between bytes.Julian Blake Kongslie2022-05-152-1/+22
* Consistent RS232 wire names (DCE side names is used everywhere)Julian Blake Kongslie2022-05-152-37/+37
* Make the calculation for OVERSAMPLE more explicit.Julian Blake Kongslie2022-05-081-1/+1
* Demand that CTS is asserted for multiple symbol periods before transmit.Julian Blake Kongslie2022-05-081-1/+8
* *Proper* serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.Julian Blake Kongslie2022-05-083-96/+133
* Oversample RS232 RX uart.Julian Blake Kongslie2022-04-222-42/+77
* Asynchronous reset on RS232 uart.Julian Blake Kongslie2022-04-221-2/+2
* Transmit and receive an even parity bit in RS232 uart.Julian Blake Kongslie2022-04-221-0/+23
* Transmit two stop bits to RS232 uart.Julian Blake Kongslie2022-04-221-2/+8
* Refer to wrap bits instead of previous greycode in FIFO greycode calculation.Julian Blake Kongslie2022-04-171-2/+2
* Working (but very slow) RS232 UARTJulian Blake Kongslie2022-04-174-31/+161
* Integrate wrap bits into grey code for FIFO.Julian Blake Kongslie2022-03-281-5/+8
* 12 PDP-8s! :-)Julian Blake Kongslie2022-03-271-1/+1
* A more-fair memory arbiter that actually works.Julian Blake Kongslie2022-03-271-31/+34
* Use the DF and IF switches as a selector for which PDP-8 owns the panel.Julian Blake Kongslie2022-03-271-89/+92
* Add a clock output pin for debugging the PLL.Julian Blake Kongslie2022-03-271-0/+3
* Reduce internal clock speed to 30MHz.Julian Blake Kongslie2022-03-271-2/+2
* Don't use SystemVerilog parametric types because Altera doesn't support them.Julian Blake Kongslie2022-03-271-9/+9
* First pass at RS232 tx/rx modules.Julian Blake Kongslie2022-03-271-0/+131
* Add basic clock-domain-crossing FIFO.Julian Blake Kongslie2022-03-261-0/+68
* Run ~*EIGHT GODDAMN PDP-8s IN PARALLEL*~Julian Blake Kongslie2022-03-202-42/+114
* Cleanup of PDP-8 core to support arbitrated memory protocol.Julian Blake Kongslie2022-03-201-190/+109
* Temporary change to PDP-8 internal memory to match controller protocolJulian Blake Kongslie2022-03-201-57/+86
* Minor paranoia about ensuring that we're in the correct half_stateJulian Blake Kongslie2022-03-181-0/+1
* Ignore colons on inputs; use them to separate words in output.Julian Blake Kongslie2022-03-182-7/+19
* Trivial change to make it a little easier to understand the mem arbiter.Julian Blake Kongslie2022-03-181-1/+1
* Change command parser to support bulk download script.Julian Blake Kongslie2022-03-131-23/+90
* Add memory arbiter and broadcast in between command UART and DRAM.Julian Blake Kongslie2022-03-133-17/+203
* Fix DRAM timings to avoid back-to-back transactions.Julian Blake Kongslie2022-03-131-3/+11
* Change FIFO size for UARTs to 1024 bytes in each direction.Julian Blake Kongslie2022-03-132-4/+4
* Print a newline after memory read result prints.Julian Blake Kongslie2022-03-131-26/+32
* Adding packed keyword to structs and tweaking tag_t slightly.Julian Blake Kongslie2022-03-131-7/+7
* Switch back to focal69 instead of broken hello.pal.Julian Blake Kongslie2022-03-011-2/+1
* Don't use the bottom data bit as the ready signal :-DJulian Blake Kongslie2022-02-281-1/+1
* Initial commit.Julian Blake Kongslie2022-02-279-0/+2033
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